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Adventurer
Adventurer
3,220 Views
Registered: ‎08-01-2017

VHDL Code of SPI to interface with TI DAC8775

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Hello Everyone!

 

I need to access DAC8775 which is from Texas Instrument, This DAC accepts data through SPI protocol,  and resolution is of 16 bits, There are certain number of registers present in DAC which I need to configure by sending data using SPI protocol,  I need vhdl code which can establish connection between FPGA and DAC8775.

Is anyone having SPI VHDL code which can interface the DAC?

 

Timing Diagram for DAC is given in the pdf file attached here with.

Thanks and Regards.

 

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1 Solution

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Contributor
Contributor
4,661 Views
Registered: ‎01-18-2013

Re: VHDL Code of SPI to interface with TI DAC8775

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Hello,

You just verify your SPI protocol whether your dac is accepting data at rising_edge or falling edge asper the timing diagram. If possible try to verify by enabling only the reference out of the dac.

--if it is useful please accept it as a solution

Best Regards,
--Ashok
2 Replies
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Xilinx Employee
Xilinx Employee
3,133 Views
Registered: ‎09-05-2007

Re: VHDL Code of SPI to interface with TI DAC8775

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@siddh4nt

I have provided a PicoBlaze reference design that can access an SPI Flash device. Note that's PicoBlaze rather than MicroBlaze so its a 'microcontroller' design popular with hardware engineers more than 'software' if you see what I mean. It also means that it implements the SPI Master signalling and the slave protocol in less than 30 Slices. I hope you find it a useful reference to adapt to your requirements.

 

https://www.xilinx.com/products/intellectual-property/picoblaze.html

 

See 'design Files' tab and download the 'KCPSM6' package. In the zip file you will find a 'Reference Designs' folder and your initial interest will be the design in the 'SPI' folder.

Ken Chapman
Principal Engineer, Xilinx UK
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Contributor
Contributor
4,662 Views
Registered: ‎01-18-2013

Re: VHDL Code of SPI to interface with TI DAC8775

Jump to solution
Hello,

You just verify your SPI protocol whether your dac is accepting data at rising_edge or falling edge asper the timing diagram. If possible try to verify by enabling only the reference out of the dac.

--if it is useful please accept it as a solution

Best Regards,
--Ashok