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Registered: ‎02-17-2020

Verifying sampling rate of XADC

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Hi, 

I am wondering how to verify the sampling rate of XADC.

I am designing an FFT, the resolution of which is dependent on the sampling rate. I used an ILA core where I get one EOC high for every 52 cycles on an 8192 ILA capture window. It is 104 for a 16834 ILA capture window. XADC DCLK frequency is 100 MHz. 

The sampling rate indicated by XADC core is 961.54 KSPS. How do I verify this rate as the ILA's x-axis is only captured BRAM cell index (1 to 8192 or 1 to 16834). Is there any other way I can verify the ADC's rate? 

Please help!

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Registered: ‎08-08-2017

Hi bhaskara@tamu.edu 

Is your ILA operating at DCLK ?

one index/Sample number in ILA corresponds to one clock cycle.

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Moderator
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Registered: ‎08-08-2017

Hi bhaskara@tamu.edu 

Is your ILA operating at DCLK ?

one index/Sample number in ILA corresponds to one clock cycle.

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Registered: ‎02-17-2020

Yes, I have the same DCLK clock of 100 MHz given to the XADC and the ILA cores. 

But here is what I have trouble in understanding: 

If one sample index on an 8192 window of ILA corresponds to one cycle of the 100 MHz clock, the same should be observed with the 16894 window ILA right? 

But when I change the capture window from 8192 to 16894 why is the position of XADC's EOC high changed to 104 from 52? (52 on 8192 capture window depth of ILA and 104 on 16894).

 

Also, I couldn't understand (in an 8192 ILA) if one EOC high pulse is asserted for 52 cycles, 100/52 > 1 MSPS. 1 MSPS being the maximum sampling rate of XADC. 

For a 16894 ILA window depth, EOC at 104th coincidentally (or not?) index matches the sampling rate. 100/104 = 961.5 KSPS is the actual sampling rate of XADC for a 100 MHz DCLK input clock.  

Please help.

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Registered: ‎04-18-2011

I have not looked too closely at this but one thing to remember is that if you have the calibration channel in the sequence, this channel is 4x longer to convert. 

 

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Registered: ‎08-08-2017

Hi bhaskara@tamu.edu 

Regarding

If one sample index on an 8192 window of ILA corresponds to one cycle of the 100 MHz clock, the same should be observed with the 16894 window ILA right?   -. Yes 

But when I change the capture window from 8192 to 16894 why is the position of XADC's EOC high changed to 104 from 52? (52 on 8192 capture window depth of ILA and 104 on 16894).

-> This is unexpected to me as well, Can you please share the ILA screenshot or .ILA files depicting the same.

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Registered: ‎02-17-2020

Hi @pthakare 

I think I made a comparison between two different ILAs operating at different frequencies while the XADC sampling rate is the same in both! 

It takes actually 104 cycles for an EOC high pulse and that makes sense. Thanks for the help!  

I'll get back if some new observation surfaces!

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