11-03-2018 08:09 AM
I am currently looking to building a Time Digital Converter in an Cmod A7-35T FPGA. I would like to realize that by a Vernier Delay line.
To build that I would need to be able to access the delay elements of the Artix 7. I would like to know how i use the delay elements
in the VHDL-Code. Alternatively I could use manual place and route to place the elements, I just don't know how to use this mode.
If possible can someone point me to an tutorial or example in how to do this?
11-05-2018 01:29 PM
11-07-2018 10:29 AM
If possible I would like to use the delay elements from a carry chain for the delay line that feeds into the D-Inputs of the D-Flipflops.
I would use no delay elements for the line that feeds into the Clock-Inputs. So I would like to wire one delay element to one D-Input
and the next delay element. To do that I would like to know how I can access these delay elements either direcly in the VHDL-Code or by manually placing them. I haven't found a way to do this either way. If this cannot be done in an Artix-7, I am willing to switch to a