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Visitor jfelix
Visitor
464 Views
Registered: ‎07-24-2018

Vernier Delay Line in an Artix 7

I am currently looking to building a Time Digital Converter in an Cmod A7-35T FPGA. I would like to realize that by a Vernier Delay line.
To build that I would need to be able to access the delay elements of the Artix 7. I would like to know how i use the delay elements
in the VHDL-Code. Alternatively I could use manual place and route to place the elements, I just don't know how to use this mode.

If possible can someone point me to an tutorial or example in how to do this?

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2 Replies
Moderator
Moderator
410 Views
Registered: ‎04-18-2011

Re: Vernier Delay Line in an Artix 7

This will be tricky to realise in the fpga.
How do you propose to create the delay elements that are described in the literature about vernier delay lines?
Something like this is not really present. Are you planning to use luts to make the delay?
In the literature one delay line drives the clock of the flip flops and the other will drive the d input.
It isn't like that in an fpga the route to the clock on these flip flops is dedicated. Using local routing is not deterministic I expect.
Are you required to match all the routing? This won't be trivial.
If that could work then you are right you will probably need to Control the placement to such an extent that you'd manually need to place everything.
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Visitor jfelix
Visitor
381 Views
Registered: ‎07-24-2018

Re: Vernier Delay Line in an Artix 7

If possible I would like to use the delay elements from a carry chain for the delay line that feeds into the D-Inputs of the D-Flipflops.
I would use no delay elements for the line that feeds into the Clock-Inputs. So I would like to wire one delay element to one D-Input
and the next delay element. To do that I would like to know how I can access these delay elements either direcly in the VHDL-Code or by manually placing them. I haven't found a way to do this either way. If this cannot be done in an Artix-7, I am willing to switch to a
different FPGA.

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