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Observer davidsummers
Observer
329 Views
Registered: ‎05-18-2015

Virtex 5 Configuration problem. INIT_B pulses low at end of bit stream.

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I am configuring a Virtex 5 FX130 device via a 16 bit wide selectmap master interface.  The FPGA does not configure properly.   

The FPGA is driving out CCLK at 2Mhz.

At 2Mhz, it should take 1.53 seconds to load the 50Mbits of configuration.     When I look at the configuration signals on a scope, at 1.53 seconds, the INIT_B signal goes low for 1.3ms.  While INIT_B is low, CCLK stops.   After 1.3ms INIT_B goes high again and then CCLK starts back up and runs forever.  The DONE pin stays low.

I understand that INIT_B going low indicates a CRC check failure, but I expected INIT_B to stay low after the CRC error.  Is it normal for configuration to start up again after 1.3ms?

I also thought that INIT_B would go low for the frame where the error occured.  Is this correct, or is there an overall CRC check at the end of the bitstream?

Signal integrity looks really good on both CCLK and the D0 - D15 data lines. 

Does anyone have any advice on the best way to debug this problem?  Any advice is appreciated.

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Observer davidsummers
Observer
249 Views
Registered: ‎05-18-2015

回复: Virtex 5 Configuration problem. INIT_B pulses low at end of bit stream.

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Thank you for your help.

The power supplies are stable, and once I fixed the error in the configuration memory that was causing the CRC errors, the FPGA configured correctly.

My confusion came from not realizing that the fallback reconfiguration option was causing INIT_B to pulse low and re-starting the configuration process.  This also resets the bits in the configuration status register, masking the fact that it was a CRC error that caused the configuration failure in the first place.

 

 

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Xilinx Employee
Xilinx Employee
308 Views
Registered: ‎08-10-2008

回复: Virtex 5 Configuration problem. INIT_B pulses low at end of bit stream.

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Yes INIT would stay low while there is a CRC error. 

CRC is a overall CRC not for a specific frame. 

The first step to debug any COnfiguration issue, is to read the the status register. So paste your STAT value here.

If your INIT_B toggles once, that sounds like an power intergraty issue, double check if any power issue, such as ground bounce on the board. Afterall, you can first read out a STAT for investigation.

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Observer davidsummers
Observer
291 Views
Registered: ‎05-18-2015

回复: Virtex 5 Configuration problem. INIT_B pulses low at end of bit stream.

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Power supplies look good.  There is no droop on 3.3, 2.5 or 1.0 during configuration.

 

Here are the results of a status register read via JTAG.   No errors are reported, but it is not configured either.

 

I also intentionally corrupted a configuration bitstream and got the same results.  INIT_B pulses low for 1.3ms and then goes high and CCLK starts up again.  I expected INIT_B to stay low due to the CRC error from the errors that i inserted.  The FPGA reacts the same way with a good bitstream or a corrupted bitstream.

 

 

 


'1': Reading status register contents...
CRC error : 0
Decryptor security set : 0
DCM locked : 1
DCI matched : 1
End of startup signal from Startup block : 0
status of GTS_CFG_B : 0
status of GWE : 0
status of GHIGH : 0
value of MODE pin M0 : 0
value of MODE pin M1 : 0
Value of MODE pin M2 : 1
Internal signal indicates when housecleaning is completed : 1
Value driver in from INIT pad : 1
Internal signal indicates that chip is configured : 0
Value of DONE pin : 0
Indicates when ID value written does not match chip ID : 0
Decryptor error Signal : 0
System Monitor Over-Temperature Alarm : 0
startup_state[18] CFG startup state machine : 0
startup_state[19] CFG startup state machine : 0
startup_state[20] CFG startup state machine : 0
E-fuse program voltage available : 0
SPI Flash Type[22] Select : 0
SPI Flash Type[23] Select : 0
SPI Flash Type[24] Select : 0
CFG bus width auto detection result : 1
CFG bus width auto detection result : 0
Reserved : 0
BPI address wrap around error : 0
IPROG pulsed : 0
read back crc error : 0
Indicates that efuse logic is busy : 0

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289 Views
Registered: ‎09-17-2018

回复: Virtex 5 Configuration problem. INIT_B pulses low at end of bit stream.

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Sounds suspiciously like it starts to run, and the power then fails,

I have seen where the power supplies are too weak to supply the required current, so as soon as it starts, it dies due to power on reset getting tripped.

Put a 'scope on the power rails (vccint, vccaux, vcco for the configuration pin bank are sensed for POR),

l.e.o.

 

Observer davidsummers
Observer
271 Views
Registered: ‎05-18-2015

回复: Virtex 5 Configuration problem. INIT_B pulses low at end of bit stream.

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Fallback reconfiguration is enable by deault for the V5 family.   I had fallback enabled, which was what was causing the strange behavior on INIT_B.   After I disabled fallback, now the INIT_B pin stays low at the end of the bitstream and the STATUS register indicates a CRC error.

 

I still have to figure out what is causing the CRC error, but at least now I understand the behavior of INIT_B.

 

Signal integrity looks really good.  the next step may be to hook up a logic analyzer and try to capture the entire bitstream and compare it to the original file.  Are there any other ways to debug configuration CRC errors? 

 

 

 

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Xilinx Employee
Xilinx Employee
259 Views
Registered: ‎08-10-2008

回复: Virtex 5 Configuration problem. INIT_B pulses low at end of bit stream.

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So you got a CRC and then triggered a fallback, that explains everything. 

Why bother to find out which bit is wrong? That's a tedious work. 

As mentioned above, this is most likely a power integrity issue, (not SI if you say so). You should monitor any drop during the whole power-up and configuration process, not just check it with a voltmeter.

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Observer davidsummers
Observer
250 Views
Registered: ‎05-18-2015

回复: Virtex 5 Configuration problem. INIT_B pulses low at end of bit stream.

Jump to solution

Thank you for your help.

The power supplies are stable, and once I fixed the error in the configuration memory that was causing the CRC errors, the FPGA configured correctly.

My confusion came from not realizing that the fallback reconfiguration option was causing INIT_B to pulse low and re-starting the configuration process.  This also resets the bits in the configuration status register, masking the fact that it was a CRC error that caused the configuration failure in the first place.

 

 

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