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apogeedbkxilinx
Adventurer
Adventurer
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Registered: ‎04-02-2010

Virtex 6 spontaneous deprogram and system monitor inaccesible

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I have a board a Virtex 6 (VC6VSX315T) FPGA.  After programming the FPGA, we find that things seem fine and we are able to get valid system monitor reads from the FPGA using chipscope.  However, after about 20 minutes the FPGA deprograms and the system monitor is no longer accessible using the chipscope tool. Here is a screen capture:

Chipscope Invalid Data

 

If we do a similar test without programming the FPGA, chipscope will be fine for a while and then spontaneously give us the same Invalid Data screen.

 

This is a mature design so we know the basic circuits are proper, however I'm at a loss as to what could cause spontaneous system monitor access problems like this.  I've checked the following

  1. VCCint is stable at 1.0V when viewed on an oscilloscope.
  2. VCCaux is stable at 2.5V when viewed on an oscilloscope.
  3. Visual inspection of the system monitor reference logic shows no missing part, etc.
  4. Confirm IC temperature is less than 30 degree Celsius when that problem occurs.

I'd appreciate any insights into what can cause a problem like this.

Regards,

David

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apogeedbkxilinx
Adventurer
Adventurer
7,541 Views
Registered: ‎04-02-2010

I'm closing this since I'm moving on to work with an FAE.

View solution in original post

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6 Replies
hpoetzl
Voyager
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Registered: ‎06-24-2013

Hey David,

 

I'd appreciate any insights into what can cause a problem like this.

I would double and triple check the (JTAG) connection to the board.

 

Especially if you are using an USB JTAG probe, check that it doesn't overheat and check with the operating system that it doesn't suddenly disappear from the bus and return with a different ID or similar.

 

Flakey USB conenctions and bad JTAG probes are one of the main reasons for FPGA debugging going wrong.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
apogeedbkxilinx
Adventurer
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Registered: ‎04-02-2010
Thanks for the input. I'm not sure how this would relate to the deprogramming of the FPGA when it is programmed, but we'll take a look.
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hpoetzl
Voyager
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Registered: ‎06-24-2013

Hey @apogeedbkxilinx,

 

Thanks for the input.

You're welcome!

 

I'm not sure how this would relate to the deprogramming of the FPGA when it is programmed

The FPGA keeps the configuration in SRAM so a power cycle or a reset on the JTAG side will undo your programming.

 

Note that it is a different story if you are observing an attached SPI or I2C memory losing its content instead of the FPGA. So if that is the case, please clarify.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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apogeedbkxilinx
Adventurer
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Registered: ‎04-02-2010
Ah. I see what you are saying about the JTAG now. By deprogramming, I am referring to the FPGA. The initial clue was a deassertion of the Done pin. We have also observed the deprogramming event occur with the JTAG cable disconnected. Would that also be consistent with a JTAG issue in your view?
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hpoetzl
Voyager
Voyager
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Registered: ‎06-24-2013

Hey @apogeedbkxilinx,

 

We have also observed the deprogramming event occur with the JTAG cable disconnected.

Would that also be consistent with a JTAG issue in your view?

No, this would hint towards a problem with the power supply or with the reset logic or insufficient power rail decoupling under heavy switching load.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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apogeedbkxilinx
Adventurer
Adventurer
7,542 Views
Registered: ‎04-02-2010

I'm closing this since I'm moving on to work with an FAE.

View solution in original post

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