UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
5,829 Views
Registered: ‎03-16-2012

Virtex 7 config fallback

Hello

 

I am having difficulty configuring the Vivado constraints to do configuration fallback for the Virtex 7. This is something that we have had working before on the Virtex 6.

 

Our configuration is as follows:

1Gbit BPI flash device

Using EMCCLK at 60MHz (clock divide by 2 so that actually running at 30MHz)

Synchronous BPI booting

RS[1:0] have pull-up resistors and connect to address lines A[25:24]

Because of the pull-up resistors, the 'standard' boot image sits at address 0x3000000.

When configuration fallback happens, RS[1:0] should pull low selecting 'golden' boot image at address 0x0

 

To test the fallback booting, I am intentially corrupting the 'standard' configuration image about half way through the image.

 

When I power the board up, I do not see the RS lines being pulled low. The Virtex 7 fails to boot but doesn't attempt to do fallback booting.

 

I think I might have a problem with my Vivado constraints. Can anyone who has gotten fallback boot working on the Virtex 7 please give the required XDC constraints?

 

I do not want any multiboot support or multiple revisions - I just want support for the fallback booting so that the FPGA can boot from the 'golden' image is something happens to the 'standard' image.

 

Any advice would be greatly appreciated.

 

Thanks

 

 

 

0 Kudos
2 Replies
Contributor
Contributor
5,822 Views
Registered: ‎03-16-2012

Re: Virtex 7 config fallback

Another question:

 

We are using compressed bit streams. Does this have any impact on whether config fallback works or not?

 

Our current constraints relating to configuration are:

set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]

set_property CONFIG_MODE BPI16 [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-2 [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE TYPE1 [current_design]
set_property BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT DISABLE [current_design]
set_property BITSTREAM.STARTUP.STARTUPCLK CCLK [current_design]
set_property LOC ICAP_X0Y1 [get_cells wishbone_flash_sdram_interface_0/icape_controller_0/ICAPE2_0]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

set_property BITSTREAM.CONFIG.REVISIONSELECT_TRISTATE ENABLE [current_design]
set_property BITSTREAM.CONFIG.TIMER_CFG 0X01000000 [current_design]

 

Am I missing something here?

0 Kudos
Moderator
Moderator
5,799 Views
Registered: ‎02-16-2010

Re: Virtex 7 config fallback

Check if the reference design for VC707 can help.
http://www.xilinx.com/support/documentation/boards_and_kits/vc707
/2014_4/xtp219-vc707-multiboot-c-2014-4.pdf
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos