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Explorer
Explorer
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Registered: ‎03-31-2016

Virtex6 IDDR/ODDR and input/output delay constraint issue

Hi

In Virtex-6 FPGA device, between IDDR/ODDR and FPGA I/O need to define set_input_delay/set_output_delay constraint? or ISE default have calculate input/output delay?

 

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Moderator
Moderator
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Registered: ‎05-02-2017

Re: Virtex6 IDDR/ODDR and input/output delay constraint issue

hi @quincyq2003

 

The Source Synchronous Dual Data Rate (DDR) case consists of an interface where the clock is regenerated inside the FPGA and sent with the data to the capturing device.
In a DDR interface, data is transmitted with both the rising and falling clock edges. In the DDR case, separate Offset Out constraints must be defined for the rising and falling clock edge registers transmitting the data. The use of the RISING and FALLING keywords with the Offset Out constraint simplifies this task. Also, for a bus skew analysis relative to the regenerated clock, the REFERENCE_PIN keyword is used.

Regards
Chandra sekhar
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