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Newbie
Newbie
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Registered: ‎07-25-2018

Where can I find the gate primitives in verilog for stanard cells?

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I was try to study a bit on the type of flops used for KC705. However where can I find the standard cells primitives verilog file in the Vivado\2014.3.1\data\parts\xilinx\kintex7 directory?

 

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Moderator
Moderator
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Registered: ‎01-16-2013

Re: Where can I find the gate primitives in verilog for stanard cells?

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@zerro_power

 

You can only use the RTL instantiation primitives of cells in Vivado. Check this link for 7 series:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug953-vivado-7series-libraries.pdf

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Highlighted
Moderator
Moderator
509 Views
Registered: ‎01-16-2013

Re: Where can I find the gate primitives in verilog for stanard cells?

Jump to solution

@zerro_power

 

You can only use the RTL instantiation primitives of cells in Vivado. Check this link for 7 series:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug953-vivado-7series-libraries.pdf

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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