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Explorer
Explorer
747 Views
Registered: ‎12-08-2007

Which clock to choose in design when on board clock source is differential LVDS ?

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I am learning Vivado on a board KC705.

This board has several clock sources.

The main one is a 2.5V LVDS differential 200 MHz oscillator.

It is a signal pair, connected to two of the FPGA pins AD12 and AD11.

Suppose I am designing a simple D Flip Flop and I wish to assign the clk signal to the clock source on the board. I choose "I/O Planning" in Vivado and I need to select the SITE for the clk signal. 

But a D-ff has a regular clock (not differential). 

To which FPGA pin should I map the signal clk?

 

thanks

 

 

 

 

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Moderator
Moderator
711 Views
Registered: ‎04-18-2011

Re: Which clock to choose in design when on board clock source is differential LVDS ?

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In this case you need to insert an IBUFDS in your code. 

This is the primitive that takes the received differential input and sends it to the fabric as a single ended signal

You can find it in the language templates in Vivado.

Hope this helps! 

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4 Replies
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Moderator
Moderator
712 Views
Registered: ‎04-18-2011

Re: Which clock to choose in design when on board clock source is differential LVDS ?

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In this case you need to insert an IBUFDS in your code. 

This is the primitive that takes the received differential input and sends it to the fabric as a single ended signal

You can find it in the language templates in Vivado.

Hope this helps! 

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Xilinx Employee
Xilinx Employee
680 Views
Registered: ‎06-02-2017

回复: Which clock to choose in design when on board clock source is differential LVDS ?

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Hi @dag1

Per klumsde said, you need to convert the differential input to a single signal, used as your system clock.

You can find the RTL template in the vivado "Language template". The attachment is the Verilog template for IBUFDS. For your reference.

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IBUFDS.JPG
Explorer
Explorer
602 Views
Registered: ‎12-08-2007

回复: Which clock to choose in design when on board clock source is differential LVDS ?

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Thanks,

I added a component called  IBUFDS_inst  : IBUFDS

one more question:

 

when I do I/O Planning I only see the signal that connects to the Positive signal of the differential pair.

I can see in the column "Neg Diff Pair" the name of the negative signal.

However, I am only given the chance to choose the FPGA Site (pin) for the Positive signal.

Will the Vivado know which SITE to connect the negative signal? Or do I need to do something different so that I can choose the SITE manually ?

 

 

 

 

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Xilinx Employee
Xilinx Employee
495 Views
Registered: ‎06-02-2017

回复: Which clock to choose in design when on board clock source is differential LVDS ?

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Hi @dag1

Yes, If you define the IOSTANDARD in the xdc as a differetial IOSTANDARD , such as LVDS. The tool will automaticlly make the negtive pin assignment if you only add the location contraint for the positive pin. 

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