02-25-2018 04:29 PM - edited 02-25-2018 04:31 PM
I'm designing a board to do something like what is described in XAPP594, "Parallel LVDS High-Speed DAC Interface". I'd put a small Artix-7 and a DAC with two 14-bit wide LVDS ports. I'd like to use OSERDES to drive the ports in 600MHz DDR mode, and output a clock.
My question is, which pins can be used for OSERDES? Is it configurable, or fixed? How do I know which P and N pins form a differential pair? I'd probably need more than one bank since I need 56 output pins, which banks should I pick?
I'm doing the hardware first, so I don't know much about the software side of this other than that app note as a starting point. I've never used OSERDES before. I read https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf but I couldn't find a direct answer to which pins to use - it seems that either Vivado would tell you when you start a design, or it doesn't matter since OSERDES is available on any pin pair.
02-26-2018 12:38 AM
There is an OSERDES for every IO in the bank. So there are 2 per pair. if you look at the UG471 doc there is the possibility to use the second OSERDES for width expansion.
Vivado can allow you to pin plan the interface. You can make a new project and select Pin Planning and not RTL.
You will be able to create an output bus and place the IOs and do a DRC.
There is only scope to have 24 pin pairs in the bank. There are 50 IOs but the top and bottom IOs are VREF sites. They can be used as IO if there no requirement on VREF, but they do not for part of a pair.
Can you clarify if you want a 600Mhz clock and 1200Mbps of DDR data or if you want a 300Mhz clock and 600Mbps of data.
It is really the clocking in the FPGA that will dictate how fast you can really go.
For Artix-7 a 600Mhz clock on the global clock buffer (BUFG) is not possible in anything but the -3 Speed Grade or -2-2LE devices with the VCCINT = 1V.
There is also a requirement on how the OSERDES is clocked.
For you, using a BUFIO will be tricky since it only spans one bank and I don't think you have a 600Mhz clock coming in to drive it with.
02-26-2018 01:19 AM
Hi @klumsde - Thank you, that is very helpful!
I'll definitely try pin planning in Vivado, good tip.
I need 600Mhz clock and 1200Mbps data. I think I would get a 600MHz clock from the DAC, I was going to connect it to a MRCC pin, is that correct?
XAPP594 talks about using BUFMR or MMCM to clock. I didn't completely understand it, but it sounds like either way would work, the MMCM way is just better.
Good to know about the speed grades; I can use a -3 or -2 here if needed.
02-26-2018 01:49 AM
So yes, if the DAC provides the a serial clock then you can use this topology.
The banks have to be adjacent to the one the MRCC is in.
BUFIO will be usable at this frequency in any speed grade.