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prushton
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Registered: ‎06-21-2012

XAPP 523 oversampling on Zynq 7010 dash 1 speed grade

Hi all,  

 

I wonder if someone can affirm my thoughts on the max oversampling rate achievable on this target as I am relatively unfamiliar with Xilinx.

 

I've ported the 4xOversampling code in this App note to a Vivado project for Zynq 7010 -1 speed grade (the Parallella board)

 

Reading the notes in the vhdl code it says to take special care for -1 and provides some example numbers as an alternative to the others grades (for the IDLY control etc) but seems to suggest it can be achieved at the 1.25Ghz rate still.   This involves Frequencies of 625Mhz and 312.5 Mhz to perform the oversampling

 

I decide to downgrade things to 1Ghz oversampling (The minimum I can get away with for this application) to give myself some headroom (so using 500Mhz and 250 Mhz frequencies) and have everything placed and constrained and meeting timing except for a pulse width violation on the BUFG component which is driving the clock to the Data Recovery unit .  On reading the spec on the BUFG in this family it appears that it can only run it's output at 464Mhz at this speed grade?   

 

This is not mentioned in the example code and would seem to limit the oversampling here at 928 Mhz (ie 2 x 464Mhz)?   Since this is required to drive the internal DRU logic it would seem to limit this device to this performance ?

 

I would be grateful if anyone out there who's familiar with oversampling and has more detailed knowledge of this device and toolset could confirm this limitation or otherwise correct my thinking :-)

 

Thanks in advance

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