04-02-2018 09:06 AM
I am running the simulation of frame clock logic of xapp524 with help of Xilinx provided testbench. There are 4 signals FrmClk, FrmClkDiv and FrmClk_p, FrmClk_N. The FrmClkDiv and FrmClk_p clock signal's frequency should be same in 1 wire mode. But in simulation case shows the different frequencies why?
Please find the attached file.
04-10-2018 02:43 AM
04-11-2018 06:36 AM
The interface is not working. I checked the design in KC705 board. When I change the mode from 2 wire to 1 wire, the frame clock should change with respect to the data rate. But in the provided design no such variation respect to wire mode.
My application is,
Wire: 1 wire
DATA: 12/14 DDR mode (240/280 Mbps data rate)