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Contributor
Contributor
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Registered: ‎10-03-2016

XAPP524 - 1 wire mode, 16 bit DDR mode - Frame clock logic

 I am running the simulation of frame clock logic of xapp524 with help of Xilinx provided testbench. There are 4 signals FrmClk, FrmClkDiv and FrmClk_p, FrmClk_N. The FrmClkDiv and FrmClk_p clock signal's frequency should be same in 1 wire mode. But in simulation case shows the different frequencies why?

 

Please find the attached file.

temp1.jpg
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Moderator
Moderator
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Registered: ‎04-18-2011

Hi, I'd need to take a closer look.
is the interface working otherwise?
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Contributor
Contributor
863 Views
Registered: ‎10-03-2016

Hi,

  The interface is not working. I checked the design in KC705 board. When I change the mode from 2 wire to 1 wire, the frame clock should change with respect to the data rate. But in the provided design no such variation respect to wire mode.

 

My application is, 

 ADC: AFE5809

Wire: 1 wire

DATA: 12/14 DDR mode (240/280 Mbps data rate)

 

Thanks,

 

 

 

Thanks,

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Contributor
Contributor
651 Views
Registered: ‎10-31-2017

in adclock.vhd line 276, the BUFR_DEVIDE is set to 4, I think this is a problem

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