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txjacob
Observer
Observer
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Registered: ‎09-23-2018

XAPP524 Data Issue

I'm working on a project with an AD9681 (125 MSPS, 14-bit, 8 channel ADC) using a Kintex-7 (XC7K325T-2FFG900C). I've downloaded the reference design for XAPP524 and I have it properly building on my board and meeting timing. However, I seem to have some problems with the startup sequence, and getting clean data. For all these pictures I am running a 1 MHz sine wave into the ADC with it running at the full 125 MSPS.

 

When I first power up the board I usually end up with something like this:

bad1.PNG

I've tied the resync input to a button on the board so I can toggle it, and if I click it again I get this waveform:

bad2.PNG

If I continue pressing the resync button I can eventually get something that looks proper, but it has a huge amount of periodic spikes

goodish1.PNG

I've got a schematic of my design here just to show what my top level block design looks like

schem.PNG

Would anyone be able to provide assistance on why my board doesn't seem to be coming up properly, and what is causing the spikes/spurs?

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klasha
Adventurer
Adventurer
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Registered: ‎05-23-2018

It looks like you are not synchronizing the reset at all. Try to add that and try again.

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txjacob
Observer
Observer
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Registered: ‎09-23-2018

klasha,

I've added the reset synchronizers like so:

schem.PNG

Now when I come out of reset the waveforms look fairly proper. However, I am still getting the odd spikes:

wv.PNG

I've put my ADC into a test output mode, and I would expect to see an alternating checkerboard like 1010101010101000, 0101010101010100. However, I'm seeing some errors in the ordering (instead I'm seeing 1010010110100100, 01011010010110):

cap1.PNG

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klumsde
Moderator
Moderator
1,462 Views
Registered: ‎04-18-2011

If you are synchronously deasserting the reset with CLKDIV then this should help. 

Are you looking at what's going on with the bitslip logic? 

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txjacob
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Registered: ‎09-23-2018

klumsde,

Which CLKDIV should I use, the one from the MMCM or the one that is derived inside of the ADC Interface logic that is derived from the frame clock? I am currently using a reset signal that is in the 200 MHz clock domain because I am running the IDELAYCTRL off of 200 MHz, while my frame clock is 125 MHz.

I have not taken a look at the bitslip logic. Let me adjust my design so I can monitor it and then I will post back with it.

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txjacob
Observer
Observer
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Registered: ‎09-23-2018

Here is the system coming out of reset with the bit slip data included.

bitslip.PNG

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txjacob
Observer
Observer
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Registered: ‎09-23-2018

So I think I may be inching towards the problem. After doing some more digging it looks like the dev board I'm using connects the FMC connector the the HR bank. I'm powering that bank off of 1.8v due to the SPI only supporting up to 2.0v. I realized I had the ports set to LVDS_25 and had the on-chip termination on too (which it looks like only works with a VCCO of 2.5v). So I turned off the termination, but I am still getting some small spurs. Unfortunately it looks like I cannot run the bank at 2.5v without getting a level shifter for the SPI...

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