02-13-2020 01:51 PM
We have developed a board using XC7A50T-CPG236 and Micron mt25ql128 memory IC for loading the RTL into FPGA at start-up. It worked well intially, however, after several read-write operations(few thousand atleast), the RTL seemed to have stopped functioning, ie, no response on the data lines. On re-programming it, it starts to work again, but fails after a while. Does anyone have any theory why the hardware would fail? I understand this is a vague question but if anyone has experienced FPGA/Memory system issues similar to what I have described here, your insight would be great.
02-14-2020 02:02 AM
Did you performed any changes in your RTL design recently?
Are you using any evalution license based Xilinx IP? Reason for this query: https://www.xilinx.com/support/answers/42380.html
02-14-2020 03:00 AM
could you let us know about your FPGA system working environment(temperature/automotive/aerospace related)? is the device you are using commercial grade or industrial grade? could you please check on your FPGA power system they remain same throughout the system functioning.
How many boards you see this issue?
03-02-2020 03:49 PM
The RTL is from a third-party vendor using an .edif core file. Could things like FPGA/oscillator clock drift affect the RTL adversely? The speed grade is -1.
03-02-2020 05:36 PM
...after several read-write operations(few thousand atleast), the RTL seemed to have stopped functioning, ie, no response on the data lines.
So, the FPGA configures itself from flash correctly, runs for a while, and then stops. Have I correctly described how things fail? -or, does the FPGA fail to configure itself from flash?
On re-programming it, it starts to work again, but fails after a while.
Do you mean that if you reprogram the flash then things start working again. -or, do you mean that when you power-cycle the board then the FPGA configures itself from flash and the FPGA starts working again?
Does anyone have any theory why the hardware would fail?
Which hardware? The flash hardware or the FPGA hardware?
Could things like FPGA/oscillator clock drift affect the RTL adversely?
Yes. If the oscillator output frequency drifts too much then CMTs like the MMCM can loose lock. If you are using the MMCM, then check other MMCM input specifications shown in Table 37 of DS181.
Do you have a constraint like the following in your .xdc file? If so, what is the value you are using for xxx?
set_property BITSTREAM.CONFIG.CONFIGRATE xxx [current_design]