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mubasheerahmed_12
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Registered: ‎08-22-2019

Z-turnlite 7z010

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Hi xilinx team. I bought z-turn lite 7z010 board. My question is. Can I write a simple code to toggle an io in VHDL and convert .bit file into .bin file and dump it into SD card and run that program? Please can anybody help this beginner? Thanks alot.
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lettertu
Xilinx Employee
Xilinx Employee
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Registered: ‎06-02-2017

Hi @mubasheerahmed_12 

You want to control an IO using the PL only, right? It's quite easy to toggle an IO by writing VHDL.

Since you're using zynq devie, if you'd like to boot the system from SD card, you have to build the FSBL.elf.  You have to create a block design to instantiate the zynq processor system to your project.

Then package the FSBL.elf and bit file in to a BOOT.bin using bootgen or in XSDK GUI.

I'd like to recommend you to refer to the following user guide for some knowledge on the embedded design using Vivado IPI folw.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug898-vivado-embedded-design.pdf

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lettertu
Xilinx Employee
Xilinx Employee
639 Views
Registered: ‎06-02-2017

Hi @mubasheerahmed_12 

You want to control an IO using the PL only, right? It's quite easy to toggle an IO by writing VHDL.

Since you're using zynq devie, if you'd like to boot the system from SD card, you have to build the FSBL.elf.  You have to create a block design to instantiate the zynq processor system to your project.

Then package the FSBL.elf and bit file in to a BOOT.bin using bootgen or in XSDK GUI.

I'd like to recommend you to refer to the following user guide for some knowledge on the embedded design using Vivado IPI folw.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug898-vivado-embedded-design.pdf

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mubasheerahmed_12
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Registered: ‎08-22-2019
That's right! Thanks for the perfect reply.sir! So you mean I can run my PL section independently and what will be my ps status while I am running PL alone will it is valid case ? Or there other procedure for that.. Okay I will check the link which you have shared to me. Thanks again.
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lettertu
Xilinx Employee
Xilinx Employee
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Registered: ‎06-02-2017

Hi @mubasheerahmed_12 

Yes, you can run the PL independently in JTAG Mode if there's a clock connected to a PL GC pin directly.

But, just as what I mentioned, if you'd like to boot the system from SD, you have to instantiate the PS in oder to generate FSBL.elf which is used to boot the system and load the bitstream to PL.

mubasheerahmed_12
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Registered: ‎08-22-2019
Okay thank you sir.
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