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Observer
Observer
5,654 Views
Registered: ‎06-24-2011

Zedboard ADC LVDS interfacing

 I am trying to interface 14bit ADC, Its single wire diffferential interface @ 4MSPS  rate clocked at DDR(Attached). I am trying to understand the XAPP524 and its vary complex and confusing. Can anyone recommend me for how to simply interface my ADC with ZYNQ on PMOD connector.

 

https://www.dropbox.com/sh/n7ahzdy2cszydr4/AADtuGbj08rV-kKxM-xbp1noa?dl=0

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Xilinx Employee
Xilinx Employee
5,635 Views
Registered: ‎08-01-2008

check this example design
https://wiki.analog.com/resources/fpga/xilinx/pmod/ad7476a

Thanks and Regards
Balkrishan
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Observer
Observer
5,632 Views
Registered: ‎06-24-2011

Hi,

thanx for your reply, I hv already gone alot of  AD reference design and they all use only single data rate for thier ADCs so they are not using SerDes/IOBUFG/ and Idelay etc.

I just need a simple example of interfacing double data rate on differential LVDS.

 

 

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Xilinx Employee
Xilinx Employee
5,628 Views
Registered: ‎08-01-2008

you can refer this XAPP target for virtex-6

XAPP1071 - Connecting Virtex-6 FPGAs to ADCs with Serial LVDS Interfaces and DACs with Parallel LVDS Interfaces Application Note ( ver1.0, 1489 KB ) [PDF]

Thanks and Regards
Balkrishan
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Observer
Observer
5,626 Views
Registered: ‎06-24-2011

Its for virtex devices but i am trying to interface with & series ZYNQ. Why this LVDS interfacing is so complex?

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