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ndw
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Registered: ‎06-22-2018

Zedboard - problem with constraints

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Good day

 

I'm using a Zedboard's XADC with an external multiplexer. I'm trying to connect the XADC wizards muxaddr_out[4:0] internal "pins" to real pins on the board using constraints. This is what I have in my .xdc file:

 

set_property PACKAGE_PIN H15 [get_ports {muxaddr_out(0)}];  # "XADC-GIO0"
set_property PACKAGE_PIN R15 [get_ports {muxaddr_out(1)}];  # "XADC-GIO1"
set_property PACKAGE_PIN K15 [get_ports {muxaddr_out(2)}];  # "XADC-GIO2"
set_property PACKAGE_PIN J15 [get_ports {muxaddr_out(3)}];  # "XADC-GIO3"
set_property PACKAGE_PIN Y11  [get_ports {muxaddr_out(4)}];  # "JA1"

set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out(0)}];
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out(1)}];
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out(2)}];
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out(3)}];
set_property IOSTANDARD LVCMOS25  [get_ports {muxaddr_out(4)}];  # "JA1"

 

(I'm using the 4 GPIO pins of the XADC and another one pmod connector pin)

 

When I generate the bitstream I get these errors below. I get these errors even when the constraints file is blank, so it looks like Vivado is not even seeing the constraints file? 

 

"[DRC NSTD-1] Unspecified I/O Standard: 5 out of 137 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: muxaddr_out[4:0].

 

[DRC UCIO-1] Unconstrained Logical Port: 5 out of 137 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: muxaddr_out[4:0]."

 

 

If someone can point me in the right direction I would really appreciate it.

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fincs
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2,062 Views
Registered: ‎03-21-2016

Hi ndw

I had similar errors with the assignment of constraints. The problem was solved by deleting the comment from the string set_property.
Also, try setting constraints through the GUI. Open Synthesized Design => Window => Package Pins (I/O Ports)

 

set_property PACKAGE_PIN H15 [get_ports {muxaddr_out(0)}];  # "XADC-GIO0"
set_property PACKAGE_PIN R15 [get_ports {muxaddr_out(1)}];  # "XADC-GIO1"
set_property PACKAGE_PIN K15 [get_ports {muxaddr_out(2)}];  # "XADC-GIO2"
set_property PACKAGE_PIN J15 [get_ports {muxaddr_out(3)}];  # "XADC-GIO3"
set_property PACKAGE_PIN Y11  [get_ports {muxaddr_out(4)}];  # "JA1"

set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out(0)}];
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out(1)}];
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out(2)}];
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out(3)}];
set_property IOSTANDARD LVCMOS25  [get_ports {muxaddr_out(4)}];  # "JA1"

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fincs
Adventurer
Adventurer
2,063 Views
Registered: ‎03-21-2016

Hi ndw

I had similar errors with the assignment of constraints. The problem was solved by deleting the comment from the string set_property.
Also, try setting constraints through the GUI. Open Synthesized Design => Window => Package Pins (I/O Ports)

 

set_property PACKAGE_PIN H15 [get_ports {muxaddr_out(0)}];  # "XADC-GIO0"
set_property PACKAGE_PIN R15 [get_ports {muxaddr_out(1)}];  # "XADC-GIO1"
set_property PACKAGE_PIN K15 [get_ports {muxaddr_out(2)}];  # "XADC-GIO2"
set_property PACKAGE_PIN J15 [get_ports {muxaddr_out(3)}];  # "XADC-GIO3"
set_property PACKAGE_PIN Y11  [get_ports {muxaddr_out(4)}];  # "JA1"

set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out(0)}];
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out(1)}];
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out(2)}];
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out(3)}];
set_property IOSTANDARD LVCMOS25  [get_ports {muxaddr_out(4)}];  # "JA1"

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ndw
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Registered: ‎06-22-2018
Also, try setting constraints through the GUI. Open Synthesized Design => Window => Package Pins (I/O Ports)

 

Thank you! This worked! 

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