UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
548 Views
Registered: ‎06-22-2018

Zynq-7 SDIO length matching

In UG933, it says:

1.pngI'm a little confused. I'm using the MIO SDIO interface to connect to SD card.

  1. It first says should place 40~60 Ohms series resistor to CLK line. Then, it says place 0 Ohm resistor in series to SDIx_CLK, where is SDIx_CLK? Is it just the SDIO_CLK?
  2. It says should control the delay between DATA(CMD) and SD_CLK within 50~200ps. Can I make them equal length? Then ideally, the delay will be 0, but the 0 delay is apparently outside of 50~200. 
Tags (2)
0 Kudos
1 Reply
Voyager
Voyager
485 Views
Registered: ‎08-16-2018

Re: Zynq-7 SDIO length matching

1 - Yes, SDx_CLK is SDIO_CLK, they just drop the 'IO' and added the x for the case you have more than one. Confusing, I agree.

It says 'place a 0 Ohm resistor that you can later change it for another value as your simulations and tests go on'. 

2 - Delay is one thing, delay skew another:

delayskw.gif

Delay skew is the variation in delays between a number of signals. Keep in mind physical length is not the same as electrical length, that is what you should equalize. I would also be surprised of stating a minimum. I would assume it means there is no point in struggling for a skew less than 50 ps.

 

0 Kudos