We use Zynq PS_MIO30,33,36 3 pins (NEXT_PWR_ENn) to control the power for the downstream port in micpod, splitter, and we use IO_L2N_TO-34(pin U12) for the same control in table hub. I know the PS_MIO30,33,36 3 pins is INPUT with a pull up to 3.3V when the Zynq boot up and loading the flash, after it, the application will set the GPIOs to OUTPUT. Now I need to make the GPIO voltage lower than 0.5V when the Zynq boot up and loading the flash so I need a resistor to pull down the GPIO.
Please help to ask Xilinx about the Zynq GPIOPS_MIO30,33,36 pull up resistance range when they are INPUT, then I could decide the pull down resistor value. And also the the GPIO output current limitation, I don't want to drain too much current from the GPIO.
Assuming a smaller part (up to '020), DS187 applies. It contains the parameter IRPU, which (for your case of VCCO = 3.3V, Vin = 0V) has limits of 90 to 330uA.
Various Xilinx sources have given contradictory explanations of the pullup - some say it is a resistor (i.e. obeys Ohm's law) and others say it it a P-channel FET that "looks like" a resistor (but probably behaves more like a current source). The datasheet doesn't say either way, and you have to assume the worst case.
Your external pulldown resistor will need to have a resistance of no more than 1.5kohm to guarantee a voltage less than 0.5V with a pullup current of 330uA.
In the high state (3.3V), this pulldown resistor will draw about 2.2mA.