02-26-2017 02:18 AM
I'm using artix xc7a100t, and i need the fpga to generate lvds iostandard to drive a device outside the fpga.
I place the differential clock in mrcc of the bank of 15, and can the vcco of bank15 be 3.3V ? I read from the datasheet from the xilinx, and it said, 'Each clock-capable input can be configured for any I/O standard, including differential I/O starddard'. Does it mean that mrcc pin can be used for any I/O standard no matter vcco is?
Another problem is xc7a100t has no HP bank, and the datasheet says lvds can only be used in HP bank. How can i generate lvds clock with xc7a100t?
Looking forward to any help. Thanks.
02-26-2017 06:57 AM
02-26-2017 08:46 AM
02-26-2017 08:47 AM
02-27-2017 12:47 AM
In my design, all the io of the fpga connected to the other device is 3.3V except the clock signal. In my system the powers are 1V, 1.8V and 3.3V. My fpga has one lvds clock outside to have the system clock and need to output a lvds clock to drive another device. In this case, most of my vcco is 3.3v, and must i use one bank of vcco 1.8v just to place two signal pins? In this bank of vcc 1.8v ,all the other pins cannot be used because they are not 3.3v standard. It's really a waste and it's difficult to route the pcb. Can't bank of vcc0 3.3v be placed lvds clock in?