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Observer kangqiaoyibie
Observer
232 Views
Registered: ‎10-07-2016

carry4 or iodelay to realize a delay line

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Hi  , I'm looking for a method to realize a delay line ,resolution <= 250ps, 39ps is more perfect.( K7-325T -2-fft900). I need 160 delay lines in my application. 

Some papers said that carry4 or iodelay can meet this application. But there some questions.

1 ,  carry4 calibration, hard to measeure each carry4 unit.  Is there any xilinx document about average delay time range of a carry4? such as 200ps ~ 300ps.

2, iodelays is attached to pads, it is hard to route and place the locations of 160 iodelays.

Any suggestion?

Thanks very much.

 

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1 Solution

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Scholar drjohnsmith
Scholar
96 Views
Registered: ‎07-09-2009

Re: carry4 or iodelay to realize a delay line

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Using internal features as delays is NOT predictable or repeatable, 

The tools are going to figth you all the way, they want to get rid of "un needed" delay elements,

 

If you string together X logic elements in the FPGA , you are going to get a delay of Dx

   If you string together a sub set of the same elements  Y in the FPGA ,  the dleay will be Yx

 

BUT, if Y is half the lenght of X, the dealy Yx can not be garunteed to be half Dx.

 Thats because the routing betwene elements is different in different parts of the chip.

 

You ask for calibration, as you can see above, its not possible to predict with any degree of certanty the delay , calibration has to be a itterative method with external test equipment,

 

 

 

 

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5 Replies
Advisor eilert
Advisor
196 Views
Registered: ‎08-14-2007

Re: carry4 or iodelay to realize a delay line

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Hi,

iodelays are intended to adapt your FPGA to the PCB.

So if you have a number of high speed I/Os routing wouldn't be a problem, since you need to connect these pins anyway.

You seem to have some special application in mind, but somehow I have the impression that you either lack some insight on how FPGAs work or have come to a wrong track for solving your problem. (You seem focussed on implementing a short delay line, but forgot about the routing delays and I/O driver delays that are much higher.)

Using (analog) delays might look like a good idea on paper, and has been used for digital systems mostly before the 80's. But it's unreliable since it varies with temperature, component tolerances etc. 

So maybe you like to share with us the original problem you have to solve. Maybe someone can give you a hint, even if that doesn't involve an FPGA.

Kind regards

  Eilert

 

Observer kangqiaoyibie
Observer
197 Views
Registered: ‎10-07-2016

Re: carry4 or iodelay to realize a delay line

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Hi eilert,

    thanks for your advice.

    Attachment is a paper described a 250ps resolution dynamic delay line, which depends on carry4. But how to calibrate carry4 (ASRPDL) under unstable temperature enviroment is un-clear for me. 

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Observer kangqiaoyibie
Observer
189 Views
Registered: ‎10-07-2016

Re: carry4 or iodelay to realize a delay line

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Attachment is xilinx paper that provide a solution for ATE , and my application is ATE . 

Multi-channels and precise delay lines are required in ATE.

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Advisor eilert
Advisor
108 Views
Registered: ‎08-14-2007

Re: carry4 or iodelay to realize a delay line

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Hi,

unfortunately your attached pdfs are somehow not accessible. (At least for me, somethings wrong with the links)

However, if you are doing ATE the delays are needed at the I/Os, arent they?

In the Zynq Product Specification (DS190) you can find this: "... by up to 32 increments of 78 ps or 52 ps each. Such delays are implemented as IDELAY and ODELAY. The number of delay steps can be set by configuration and can also be incremented or decremented while in use."

So, since you have to route your I/Os anyway to some given pin, that pins I/O delay can be used and even adapted while in use.

Carry-lines have short delays, but are probably not useful for your application. The routing to and from the carry line has more delay than the carry line itself and is different on each tap.

Here's a link to another thread dealing with Carry-Delays:

https://forums.xilinx.com/t5/Virtex-Family-FPGAs-Archived/tapped-delay-line/m-p/309203#M16301

Check the whole thread (3 posts) to fully understand the topic.

------

It would be good to know where in your signal path the delay is needed.

If it is on the inputs or outputs and dhe builtin delays are too coarse, maybe you should thing about an external solution.

There are programmable digital resistors available. Putting them in series to some I/O can cause a programmable delay together with the line and I/O capacity. However this requires good understanding of the outer circuitry and PCB properties of your intended device.

 

Kind regards

  Eilert

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Scholar drjohnsmith
Scholar
97 Views
Registered: ‎07-09-2009

Re: carry4 or iodelay to realize a delay line

Jump to solution

Using internal features as delays is NOT predictable or repeatable, 

The tools are going to figth you all the way, they want to get rid of "un needed" delay elements,

 

If you string together X logic elements in the FPGA , you are going to get a delay of Dx

   If you string together a sub set of the same elements  Y in the FPGA ,  the dleay will be Yx

 

BUT, if Y is half the lenght of X, the dealy Yx can not be garunteed to be half Dx.

 Thats because the routing betwene elements is different in different parts of the chip.

 

You ask for calibration, as you can see above, its not possible to predict with any degree of certanty the delay , calibration has to be a itterative method with external test equipment,

 

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post