UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
464 Views
Registered: ‎10-06-2018

fir filter output

Hi,

 I written Verilog code for FIR filter by circular convolution with 1K samples, but its taking settling time for every cycle, i am unable to find out the problem any body can suggest me 

Screenshot (4).png
0 Kudos
3 Replies
Voyager
Voyager
457 Views
Registered: ‎08-16-2018

Re: fir filter output

you must be flushing your pipeline or resetting it somehow. Is it vhdl/ verilog you could share?

0 Kudos
432 Views
Registered: ‎10-06-2018

Re: fir filter output

thank you for ur reply sir,

   ya what u told its correct only, I am resetting it at k=1023 (sample size is 1k).

if I didn't reset it at k=1023, the result will add to previous output and my waveform its look like ramp sine wave. so I am resetting it. 

0 Kudos
Voyager
Voyager
427 Views
Registered: ‎08-16-2018

Re: fir filter output

narendrandesainath@gmail.com

So I guess this is the cause of your settling time, FIR filters have latency. Below is a FIR filter (one of the implementations). After a reset, you need to clock data N times to have an actual value at the output of the last delay box, otherwise you have zero.

1000px-FIR_Filter.svg.png

0 Kudos