10-16-2018 05:30 AM
I written Verilog code for FIR filter by circular convolution with 1K samples, but its taking settling time for every cycle, i am unable to find out the problem any body can suggest me
10-16-2018 05:58 AM
10-16-2018 11:58 PM
thank you for ur reply sir,
ya what u told its correct only, I am resetting it at k=1023 (sample size is 1k).
if I didn't reset it at k=1023, the result will add to previous output and my waveform its look like ramp sine wave. so I am resetting it.
10-17-2018 12:56 AM - edited 10-17-2018 12:57 AM
So I guess this is the cause of your settling time, FIR filters have latency. Below is a FIR filter (one of the implementations). After a reset, you need to clock data N times to have an actual value at the output of the last delay box, otherwise you have zero.