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Visitor
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Registered: ‎07-08-2009

how to set a pipeline for xpm_sync_fifo using ultra ram type?

Hi, I'm using xpm_sync_fifo and meet a output pipeline issue. The xpm_sync_fifo is "fwft" read mode, and the FIFO_MEMORY_TYPE is "ultra". The compile report show that the fifo output pipeline is 0. And the fifo cannot meet the timing constraint. The compile report is attached. How can I set the xpm fifo output pipeline when it's fwft mode? Thanks
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Visitor
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Registered: ‎07-08-2009

The compile report is here.
Ultra RAM: Preliminary Mapping Report (see note below)
+----------------------------------------------------------------------------------------+-------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+---------+--------------+--------------------------+-------------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | URAM288 | Matrix Shape | FF provided for Pipeline | FF absorbed |
+----------------------------------------------------------------------------------------+-------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+---------+--------------+--------------------------+-------------+
|data_fifo_inst/xpm_fifo_sync_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 4 K x 36 | W | | 4 K x 36 | | R | Port A and B | 1 | 1x1 | 0 | 0 |
|sync_fifo_ftdc/xpm_fifo_sync_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 32 K x 37 | W | | 32 K x 37 | | R | Port A and B | 8 | 8x1 | 0 | 0 |
|data_fifo_inst/xpm_fifo_sync_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst | gen_wr_a.gen_word_narrow.mem_reg | 4 K x 36 | W | | 4 K x 36 | | R | Port A and B | 1 | 1x1 | 0 | 0 |
+----------------------------------------------------------------------------------------+-------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+---------+--------------+--------------------------+-------------+
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Moderator
Moderator
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Registered: ‎08-08-2017

Hi @tohust 

Number of output register stages in the read data path is set using "FIFO_READ _LATENCY " paramater , but as your read_mode is set to "fwft" you can not have

register stages on output.

Btw what is the clk rate here ?

FYI , we have guidance on setting the register stages as per your implementation. See the below blog

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Achieving-optimal-timing-performance-by-automatic-pipelining-of/ba-p/971760

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