05-11-2020 11:59 PM
05-12-2020 12:04 AM
06-05-2020 05:00 AM
Number of output register stages in the read data path is set using "FIFO_READ _LATENCY " paramater , but as your read_mode is set to "fwft" you can not have
register stages on output.
Btw what is the clk rate here ?
FYI , we have guidance on setting the register stages as per your implementation. See the below blog