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Adventurer
Adventurer
243 Views
Registered: ‎09-21-2019

io_pin testing

Hello All,

I am using zynq 7000 customize board.In that a pin which is on bank 35 (FPGA) is taken on connector(j3).J3 connector is 7 pin connector in which 7 no. pin is ground.

I am testing all io's by writing counter code.

I am getting waveforms on DSO for  all pins except  6 no. pin.

I have added then chipscope .On chipscope i am getting the waveform but not on DSO.

What can be the reason ?

 

 

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3 Replies
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212 Views
Registered: ‎06-21-2017

Re: io_pin testing

You may have a manufacturing problem.  Either a ball is not soldered to a pad, the line could be shorted or, more rarely, a via might be cracked.

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Adventurer
Adventurer
171 Views
Registered: ‎09-21-2019

Re: io_pin testing

@bruce_karaffa Thanks for reply.

If i want to do boundary scan then how would i do to check the pin?

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Registered: ‎06-21-2017

Re: io_pin testing

I don't think Xilinx provides any boundary scan features for users.  You need to debug the old fashioned way.  Did you have the BGAs xrayed after assembly?  This can sometimes show a bad solder joint on a ball. If you push down lightly on the Zynq, does the signal appear?  Sometimes you can find a bad solder connection this way.  Can you find the via under the Zynq?  Probe it with a scope.  Sometimes traces break where they connect to vias.  If there is a signal there, the trace is broken somewhere.  You also have to consider the possibility of ESD damage to the driver on the Zynq.  How careful were you when handling and probing the board? 

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