cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
6,368 Views
Registered: ‎06-07-2011

odelaye2 wrong tap resolution

Jump to solution

I'm using some XC7Z030's odelaye2, to delay signals. I instantiated the idelayctrl too. The clock frequency is 200 MHz. Accordingly DS182
"Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics" The step resolution should be 78.5 ps but it is twice this value, 157 ps. Therefore the max delay I can introduce is about 5 ns.

 

This is my instantion:

 

 m_odelay: ODELAYE2
    generic map(
      CINVCTRL_SEL          => "FALSE",
      DELAY_SRC             => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      ODELAY_TYPE           => "VARIABLE",
      ODELAY_VALUE          => 0,
      PIPE_SEL              => "FALSE",
      REFCLK_FREQUENCY      => 200.0,
      SIGNAL_PATTERN        => "DATA")
    port map(
      CNTVALUEOUT => s_odelay_value,
      DATAOUT     => s_tick,
      C           => i_rx_usr_clk,
      CE          => s_CE,
      CINVCTRL    => s_CINVCTRL,
      CLKIN       => s_CLKIN,
      CNTVALUEIN  => s_CNTVALUEIN,
      INC         => s_INC,
      LD          => s_LD,
      LDPIPEEN    => s_LDPIPEEN,
      ODATAIN     => i_delay_data,
      REGRST      => s_REGRST);

 

What I'm doing wrong? It's not the first time I'm using an odelay.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Observer
Observer
11,213 Views
Registered: ‎06-07-2011

I solved the problem, by extending the reset.

 

Tom

View solution in original post

0 Kudos
7 Replies
Highlighted
Xilinx Employee
Xilinx Employee
6,352 Views
Registered: ‎02-14-2014

Hello @abaxor,

 

As per datasheet below, the tap resolution when REFCLK _FREQUENCY is 200 MHz is 78 ps.

http://www.xilinx.com/support/documentation/data_sheets/ds191-XC7Z030-XC7Z045-data-sheet.pdf (page #52)

 

Can you share complete design here to have a look where exactly delay values went wrong?

Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Observer
Observer
6,325 Views
Registered: ‎06-07-2011

Hi Ashish ,

 

I uploaded the project, reduced to the odelay problem. I verified it with the scope. Still present.

 

Thanks Tom

 

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
6,286 Views
Registered: ‎02-14-2014

Hello @abaxor,

 

I have checked the design. ODELAYE2 component is used in restrig_fine.vhdl and deltrig_fine.vhdl files. Did you observe same behavior with both of the files? It seems that you haven't shared testbench to verify the functionality. Can you check if you are getting correct delays in simulation (using testbench) before moving to hardware verification?

Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Highlighted
Observer
Observer
6,266 Views
Registered: ‎06-07-2011
Hi Ashish, yes odelaye2 is used in 2 components. I use it in a more complex project. This one I have simulated and achived 78 ps tap delay. The same design has been evaluated on a ZC706, even with a tap delay of 78 ps. I did not simulate the example I preprared for you. Best Regards, Tom
0 Kudos
Highlighted
Observer
Observer
11,214 Views
Registered: ‎06-07-2011

I solved the problem, by extending the reset.

 

Tom

View solution in original post

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
6,068 Views
Registered: ‎08-01-2012

 

@abaxor Thanks for sharing the information for other forum users benefit. 

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

0 Kudos
Highlighted
Adventurer
Adventurer
453 Views
Registered: ‎01-24-2018

 

Tom, 

 

Because I am facing the same issue like you did, could you please to share us more information about how to solve this issue?

You mentioned that "I solved the problem, by extending the reset."

What reset did you extended? is idelayctrl's reset?

 

Thank you very much in advance!

0 Kudos