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Observer abaxor
Observer
6,101 Views
Registered: ‎06-07-2011

odelaye2 wrong tap resolution

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I'm using some XC7Z030's odelaye2, to delay signals. I instantiated the idelayctrl too. The clock frequency is 200 MHz. Accordingly DS182
"Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics" The step resolution should be 78.5 ps but it is twice this value, 157 ps. Therefore the max delay I can introduce is about 5 ns.

 

This is my instantion:

 

 m_odelay: ODELAYE2
    generic map(
      CINVCTRL_SEL          => "FALSE",
      DELAY_SRC             => "ODATAIN",
      HIGH_PERFORMANCE_MODE => "FALSE",
      ODELAY_TYPE           => "VARIABLE",
      ODELAY_VALUE          => 0,
      PIPE_SEL              => "FALSE",
      REFCLK_FREQUENCY      => 200.0,
      SIGNAL_PATTERN        => "DATA")
    port map(
      CNTVALUEOUT => s_odelay_value,
      DATAOUT     => s_tick,
      C           => i_rx_usr_clk,
      CE          => s_CE,
      CINVCTRL    => s_CINVCTRL,
      CLKIN       => s_CLKIN,
      CNTVALUEIN  => s_CNTVALUEIN,
      INC         => s_INC,
      LD          => s_LD,
      LDPIPEEN    => s_LDPIPEEN,
      ODATAIN     => i_delay_data,
      REGRST      => s_REGRST);

 

What I'm doing wrong? It's not the first time I'm using an odelay.

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1 Solution

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Observer abaxor
Observer
10,946 Views
Registered: ‎06-07-2011

Re: odelaye2 wrong tap resolution

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I solved the problem, by extending the reset.

 

Tom

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7 Replies
Xilinx Employee
Xilinx Employee
6,085 Views
Registered: ‎02-14-2014

Re: odelaye2 wrong tap resolution

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Hello @abaxor,

 

As per datasheet below, the tap resolution when REFCLK _FREQUENCY is 200 MHz is 78 ps.

http://www.xilinx.com/support/documentation/data_sheets/ds191-XC7Z030-XC7Z045-data-sheet.pdf (page #52)

 

Can you share complete design here to have a look where exactly delay values went wrong?

Regards,
Ashish
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Observer abaxor
Observer
6,058 Views
Registered: ‎06-07-2011

Re: odelaye2 wrong tap resolution

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Hi Ashish ,

 

I uploaded the project, reduced to the odelay problem. I verified it with the scope. Still present.

 

Thanks Tom

 

 

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Xilinx Employee
Xilinx Employee
6,019 Views
Registered: ‎02-14-2014

Re: odelaye2 wrong tap resolution

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Hello @abaxor,

 

I have checked the design. ODELAYE2 component is used in restrig_fine.vhdl and deltrig_fine.vhdl files. Did you observe same behavior with both of the files? It seems that you haven't shared testbench to verify the functionality. Can you check if you are getting correct delays in simulation (using testbench) before moving to hardware verification?

Regards,
Ashish
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Observer abaxor
Observer
5,999 Views
Registered: ‎06-07-2011

Re: odelaye2 wrong tap resolution

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Hi Ashish, yes odelaye2 is used in 2 components. I use it in a more complex project. This one I have simulated and achived 78 ps tap delay. The same design has been evaluated on a ZC706, even with a tap delay of 78 ps. I did not simulate the example I preprared for you. Best Regards, Tom
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Observer abaxor
Observer
10,947 Views
Registered: ‎06-07-2011

Re: odelaye2 wrong tap resolution

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I solved the problem, by extending the reset.

 

Tom

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Xilinx Employee
Xilinx Employee
5,801 Views
Registered: ‎08-01-2012

Re: odelaye2 wrong tap resolution

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@abaxor Thanks for sharing the information for other forum users benefit. 

________________________________________________

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Adventurer
Adventurer
186 Views
Registered: ‎01-24-2018

Re: odelaye2 wrong tap resolution

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Tom, 

 

Because I am facing the same issue like you did, could you please to share us more information about how to solve this issue?

You mentioned that "I solved the problem, by extending the reset."

What reset did you extended? is idelayctrl's reset?

 

Thank you very much in advance!

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