06-18-2018 07:01 PM
I need to generate a variety of clocks from a given reference clock and then multiplex them and send to a
single input clock source to the design. As cascading BUFG gives rotuing errors, I'm planning to use a
programmable MMCM which when configured, generates a single MMCM output clock.
Does Xilinx have a programmable MMCM module ?
06-18-2018 07:20 PM
All MMCMs have a "Dynamic Reconfiguration Port" (DRP). The DRP port exists on all MMCMs, but is "hidden" if you instantiate an MMCME2_BASE instead of an MMCME2_ADV, but both target the same MMCME2 on the die. The DRP is a control interface that has address (DADDR), data in (DIN), clock (DCLK), enable and write enable (DEN and DWE).
Using the DRP is not trivial - you need to manage the register map of the MMCM, and, in most cases, reset the MMCM after you have finished reprogramming it. Reprogramming it often requires the changing of multiple regsters. Driving the DRP will either require an internal processor (i.e. a Zynq, or MicroBlaze), or an external interface from a microcontroller that drive the DRP through a register interface, or a state machine that will drive the DRP interface.
The documentation on using the DRP is available in UG472 and XAPP888 (for the 7 series).
06-18-2018 07:34 PM
Let me explain my design, so that you can give a better solution
Our ASIC design works on a variety of source clocks to JESD 204B transmitter design and the destination clock
of the JESD204B transmitter is fixed. The design has FIFOs take care of the various input rates.
The source clock frequency depends on the effective sampling rate to the transmitter.
For us to validate this in FPGA, we need to create a variety of such scenarios, each scenario
operating on a specific frequency. There are 8 such clock scenarios.
The design gets a single clock source input that is the mux output of these 8 clocks.
The requirement is, from reset to reset, the input clock frequency remains the same, so there is no
dynamic frequency change on the fly.
The frequencies to be muxed (in MHz) are 15.6125, 20.833, 31.25, 41.667, 62.5, 83.333, 103.25, 125.
The reference clock frequency to the MMCM = 156.25 MHz
Alternatively, it is also okay to have a programmable MMCM that gets a control port which the user can change.
How do we achieve this?
06-21-2018 03:14 PM
Yes, you can use the MMCM to configure up to 8 outputs, each with a different frequency and phase.
In your case, you could have the MMCM output all those frequencies at the same time and create your own logic to multiplex and select the frequency you want your design to use at a given time.
I see that many frequencies are a multiple of another, so you might have the MMCM output only 4 or 5 frequencies and further divide them with a BUFGCE_DIV.
One third alternative is to use the MMCM and have it output a single frequency at a time, and use a DRP to reconfigure the MMCM and have it shift to a different frequency when necessary.
Please take a look at the document UltraScale Architecture Clocking Resources - UG572, starting on pg. 35 for all the MMCM features and configurations.
And if you go the Dynamic Reconfiguration (DRP) route, please take a look at the document MMCM and PLL Dynamic Reconfiguration - XAPP888.
06-22-2018 12:15 AM - edited 06-22-2018 12:16 AM
I am using MMCM in programmable mode. I use so called cascade mode where two outputs are cascaded (OUT 4 and OUT 6) to achieve also lower output frequencies (VCO divided two times, A and B divider). All you have to do is to calculate 4 parameters (A, B, D and fractional M). I do this in Python and write them via USB to the FPGA. Actually I write 5 parameters, because M has two parts - integer and fractional part. It is also possible to calculate them in HDL or C (in Microblaze let say). All files which works for me are included... Hope it will work for you.
PS: I changed files to .txt because I couldn't attach SystemVerilog .sv types.