1. can I connect a 2.5v output driver to 3.3v bank? from voltage levels its a bit on the limit (2.2-2.3 volt out from device to 2v vih in the fpga).
2. if the signal is clock a(2.5v device levels as above mantioned) and i connect it to gclk input of 3.3v bank, is the answer is different?what are the clock voltage levels determine to set the desicion when its rising or falling (vcco/2 ?)
I doubt that you will damage the chip, but I can think of a couple possible problems if you use a 2.5V signal as a clock on a 3.3V input. You will reduce the noise immunity of the high side of the signal. It will be more likely to false trigger if you have any ringing on the input. The duty cycle will no longer be 50%. This may or may not be a problem. The jitter on the internal clock will be higher. The input voltage will be starting to flatten out as it is going through the transition point, making the clock more succeptable to random voltage noise on the input.