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Visitor a06014625
Visitor
564 Views
Registered: ‎10-03-2018

warming: Bus 'data_q(15:0)' is connected to too many source pins and/or I/O markers

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I'm new of fpga. What I'm doing is use the 'ram16x8s' memory for expansion. But i meet a problem when I use the check schematic and get the warning "Start DRC ...
WARNING:DesignEntry:220 - ram_64x16.sch Bus 'data_q(15:0)' is connected to too many source pins and/or I/O markers.
A total of 0 error(s) and 1 warning(s) were detected" 

What's the problem of my bus signal'data_q(15:0)'?

 

Thanks!

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Scholar drjohnsmith
Scholar
549 Views
Registered: ‎07-09-2009

Re: warming: Bus 'data_q(15:0)' is connected to too many source pins and/or I/O markers

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The rams you have have outputs  , always enabled

     which you have joined together,

 

QED , each output bit has two drivers, and as such is an error.

 

you need to use an address bit to select which of the two rams to output at any one time.

   

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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2 Replies
Scholar drjohnsmith
Scholar
550 Views
Registered: ‎07-09-2009

Re: warming: Bus 'data_q(15:0)' is connected to too many source pins and/or I/O markers

Jump to solution

The rams you have have outputs  , always enabled

     which you have joined together,

 

QED , each output bit has two drivers, and as such is an error.

 

you need to use an address bit to select which of the two rams to output at any one time.

   

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Visitor a06014625
Visitor
480 Views
Registered: ‎10-03-2018

Re: warming: Bus 'data_q(15:0)' is connected to too many source pins and/or I/O markers

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Thank you!
Have a nice day.

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