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Newbie
Newbie
5,578 Views
Registered: ‎04-18-2017

what's the difference between GTX and regular I/O?

Hi, total newbie here. I understand that GTX/GTH (and the like) are serial interfaces, they have transceivers, do encoding etc, but are they internally at the lowest level connected the same way regular I/O is? Could the regular I/O achieve the same bandwidth theoretically as GTX if all the transceivers are implemented externally, or encoding and serialization is implemented externally? My understanding of it is that yes, that GTX is just a layer on the existing I/O, and the point of it is to provide another "service" to make certain things easier for certain applications, otherwise it wouldn't make sense for some I/O to be faster and some be slower. Is that right?

 

Thanks

-Ion

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Newbie
Newbie
5,569 Views
Registered: ‎04-18-2017

To add something to this (could not find a way to edit my previous post), if you were to implement a high speed serial interface like PCIe or USB 3.1, could you do it without GTX? You'd probably need some external parts due to the shape of the signal itself, but could you do it, for the most part? Without an USB 3.1 ASIC or anything like that, that would be cheating. My question is coming purely from a curiosity standpoint, to understand FPGAs better.

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Advisor
Advisor
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Registered: ‎04-26-2015

You could certainly use an external serializer/desserializer IC on the general-purpose I/O pins to achieve a similar result. For example, you could use 32 pins and a TI DS92LV16 to effectively get a 2.56Gbps transceiver.

 

The GTX/GTH/GTY transceivers just shift all of that functionality on-chip, which saves board space, saves pins on the FPGA (for the 30Gbps+ transceivers on FPGAs, you'd need several hundred parallel pins), and gives you far more flexibility (ie able to easily change registers to adjust transceiver settings).

 

As for whether you could achieve the same speed through regular I/O pins: no! The transceivers use dedicated hardware to drive those I/Os much faster, and to do that they've had to cut out almost all of the highly-flexible I/O circuitry that the GPIO pins have. You can go pretty fast with GPIOs anyway (over 1Gbps) but for very high speeds the dedicated hardware is essential.

 

To implement USB3.1 over GPIOs, you'd have to use a dedicated SerDes chip (as mentioned above). Cypress makes a range of USB3.0-to-parallel chips that are quite popular in low-budget, high-bandwidth FPGA applications.

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Newbie
Newbie
5,546 Views
Registered: ‎04-18-2017

I guess another way to word my question is, how is the GTX transceiver connected to the FPGA fabric, compared to regular I/O, and is there something in the way it is connected there that would make it faster that a regular I/O path

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Newbie
Newbie
5,536 Views
Registered: ‎04-18-2017

Thank you for the explanation, that clarifies things, and the USB parallel chips is a good example, you could use easily use an FX3 and send the data over a parallel interface from the FPGA, that just illustrates that 5Gbps should be no problem. Cumulatively it seems that you could achieve quite high bandwidth over a parallel interface. I'm just wondering how fast can you get, is the 1Gbps number for a single I/O pin?

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Xilinx Employee
Xilinx Employee
5,535 Views
Registered: ‎08-01-2008

check this XAPP
https://www.xilinx.com/support/documentation/application_notes/xapp1200-k7-xcvr-wiz-example-design.pdf
Thanks and Regards
Balkrishan
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Advisor
Advisor
5,487 Views
Registered: ‎04-26-2015

The fastest single-ended parallel interface you'll see on GPIO pins is for RAM. On the Zynq 7000 (and Artix 7) chips you can get this as high as 1066Mbps per pin (although that has pretty specific requirements). Ultrascale+ chips can go up to 2666Mbps per pin. You can definitely achieve very high bandwidth over such an interface - several Zynq Ultrascale+ boards allow for over 170Gbps via a 64-bit parallel DDR4 connection. The downside of this approach is that breaking out a 64-bit bus from under a BGA chip, while meeting all of the impedance and trace length requirements, is very difficult. I suspect that the boards doing this are at least 12-layer, possibly more like 16.

 

The on-chip transceivers are effectively connected to internal parallel GPIO pins, although obviously these internal pins don't have the fancy I/O circuitry used for external pins. Because it's all internal you don't have to worry about routing a huge, fast bus around the PCB - there are just two differential pairs instead.

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