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Observer micrelrogerlo
Observer
407 Views
Registered: ‎09-18-2013

what's the maximum clock domain signal could be debugged in ila debug core?

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Hi,

     I am using xc7v2000tflg1925-2 FPGA device. I am just wondering if it would be okay to debug signals which are in 312.5 MHz clock domain by using ILA core. If yes, what would be the speed limit in ILA core?

Thanks,

Roger Lo

 

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Moderator
Moderator
368 Views
Registered: ‎08-08-2017

Re: what's the maximum clock domain signal could be debugged in ila debug core?

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Hi @micrelrogerlo 

You need to consider the Fmax of the device .(Fmax of the device is decided based on maximum supported frequency by global buffer (BUFG)

To debug/sample 312.5MHz signal in the ILA, the ILA should be run at min 625MHz accodring to sampling theorem.

as you are using -2 speed grade device, the Fmax of the device is 710Mhz, so it will not be any problem with your approach

Capture.JPG

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6 Replies
Moderator
Moderator
390 Views
Registered: ‎11-04-2010

Re: what's the maximum clock domain signal could be debugged in ila debug core?

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Hi, @micrelrogerlo ,

There is no explicit speed limit for the ILA core. 

If there is no timing violation after inserting the ILA core, it should work.

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Moderator
Moderator
369 Views
Registered: ‎08-08-2017

Re: what's the maximum clock domain signal could be debugged in ila debug core?

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Hi @micrelrogerlo 

You need to consider the Fmax of the device .(Fmax of the device is decided based on maximum supported frequency by global buffer (BUFG)

To debug/sample 312.5MHz signal in the ILA, the ILA should be run at min 625MHz accodring to sampling theorem.

as you are using -2 speed grade device, the Fmax of the device is 710Mhz, so it will not be any problem with your approach

Capture.JPG

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Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
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Mentor hgleamon1
Mentor
365 Views
Registered: ‎11-14-2011

Re: what's the maximum clock domain signal could be debugged in ila debug core?

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Surely the ILA core should be clocked by the same 312.5 MHz clock that those signals marked for debug are clocked by?

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"That which we must learn to do, we learn by doing." - Aristotle
Observer micrelrogerlo
Observer
345 Views
Registered: ‎09-18-2013

Re: what's the maximum clock domain signal could be debugged in ila debug core?

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Hi Hongh,

     Thanks for sharing your opinion.

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Observer micrelrogerlo
Observer
342 Views
Registered: ‎09-18-2013

Re: what's the maximum clock domain signal could be debugged in ila debug core?

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Hi Hgleamon1,

    Thanks for your reminding.

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Observer micrelrogerlo
Observer
341 Views
Registered: ‎09-18-2013

Re: what's the maximum clock domain signal could be debugged in ila debug core?

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Hi Pthakare,

    The information is very helpful. Thanks so much.

 

 

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