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Visitor vishwajit_01
Visitor
723 Views
Registered: ‎05-09-2018

Artix -7 floating pins

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Hi, I am using Artix 7 :  "XC7A50T-1FGG484I" FPGA. There are few pins as follows :

1. VCCO_13_1
2. VCCO_13_2

3. VCCO_13_3

4. VCCO_13_4

5. VCCO_13_5

In the package pinout file it is mentioned that these pins belong to bank 13 but except for these pins there are no other pins in bank 13.

A) My doubt is what to do with these pins?

B) Can I leave these pins floating?

C) Should I connect some voltage to it then what must be the voltage value & should I connect de-coupling capacitors to the above mentioned pins?

 

 

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1 Solution

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Community Manager
Community Manager
659 Views
Registered: ‎07-23-2015

Re: Artix -7 floating pins

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@vishwajit_01 VCCO_13 pins are provided in case you plan to migrate to higher density devices i.e. A75T and A100T in the same package FGG484 which have the Bank 13 partially bonded out. So if you have plans to migrate or if not sure at this point of time, connect VCCO_13 to a suitable voltage rail. It is always recommended to connect unused VCCO pins to either a power plane or GND for better ESD protection. 

 

In your case, better to have it connected to a VCCO rail as it offers you flexibility down the line. 

 

 

- Giri
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11 Replies
Scholar drjohnsmith
Scholar
710 Views
Registered: ‎07-09-2009

Re: Artix -7 floating pins

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VCCO are power pins

 

if bank 13 exists in that package, they need to be connected ,

 

 Ive just checked the pin out file, and , yes there is a bank 13 in the power section, not the IO setion !

 

 

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Voyager
Voyager
691 Views
Registered: ‎08-16-2018

Re: Artix -7 floating pins

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If you have I/O pins in a bank, you have VCCO pins for that bank. The opposite is also true.

If you are not using a bank (I think) you can tie its VCCO pins to GND. That will only affect the I/Os, you still will have the same LBs available

The general rule in electronics is not to leave input pins open but to tie them to ground or to a power rail.

Open input pins may pick up ESD and misfunction or even destroy the chip, not that much the case with power pins, but better to be safe.

For FPGAs, being flexible, is not very smart not to power a bank as you may need it in the future and will have to re-spin your PCB.

Output or non-configured (Hi-Z) I/O pins can be left open. Actually, must not be tied to any rail.

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Scholar drjohnsmith
Scholar
678 Views
Registered: ‎07-09-2009

Re: Artix -7 floating pins

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Had a look into this

 

no clear answer, 

    but bank 13 s a HR bank, 

 

so even though you have no IO pined out on bank 13, 

   I'd suggest you connect them to 1v8 or similar you have in your design already.

 

 

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Scholar drjohnsmith
Scholar
673 Views
Registered: ‎07-09-2009

Re: Artix -7 floating pins

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As a suggestion

 

I have had a look around at demo boards,

 

ones such as this tie these pins to a Vcc voltage

 

https://numato.com/help/wp-content/uploads/2018/06/MimasA7_Sch.pdf

 

but it does seem an interesting problem that the documentation seems to miss,

 

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Community Manager
Community Manager
660 Views
Registered: ‎07-23-2015

Re: Artix -7 floating pins

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@vishwajit_01 VCCO_13 pins are provided in case you plan to migrate to higher density devices i.e. A75T and A100T in the same package FGG484 which have the Bank 13 partially bonded out. So if you have plans to migrate or if not sure at this point of time, connect VCCO_13 to a suitable voltage rail. It is always recommended to connect unused VCCO pins to either a power plane or GND for better ESD protection. 

 

In your case, better to have it connected to a VCCO rail as it offers you flexibility down the line. 

 

 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
Scholar drjohnsmith
Scholar
641 Views
Registered: ‎07-09-2009

Re: Artix -7 floating pins

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Mr Moderator

 

I think it would be good to add this to the documentation as it is less than clear,

 

or at least a clearly indexed answer record ( Vcco bank 13 Artix 50 ? )

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Community Manager
Community Manager
634 Views
Registered: ‎07-23-2015

Re: Artix -7 floating pins

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@drjohnsmith We do have it in UG475 7-series package guide

vcco_unbonded.jpg


 or at least a clearly indexed answer record ( Vcco bank 13 Artix 50 ? )


We have an AR too :)

https://www.xilinx.com/support/answers/59393.html which I missed to include in earlier post. 

Can't index it to Artix 50T/VCCO_13 since the guideline is applicable to any package/device which has VCCO pins in unbonded bank

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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Scholar drjohnsmith
Scholar
624 Views
Registered: ‎07-09-2009

Re: Artix -7 floating pins

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@gnarahar

 

I would class that as an object guide into how to be very un clear.

 

The orriginal poster, and all others have stated that yes, this is a power supply,

    and yes it needs to be tied to something

 

but 

 

Normaly a user would say , ah yes, bank 13 IO is connected to bank 13 VCCo, so I know I need it to be X volts,

 

BUT as the user orrinlay pointed out, in some packages , you have banks that have Power but NO IO pins,

    hence there question,  

 

To be clear I would hope that you could make an answer record for these  packages , easily find-able, that answers the question of what are these un used VCC pins for / to be tied to.

 

The very fact that quite a few of us , who have been around the block could not find the answer says that the documentation is un clear and there is not an answer record that can be easily found,   and Xilinx could easily improve bu making a simple answer record.

 

 

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Community Manager
Community Manager
618 Views
Registered: ‎07-23-2015

Re: Artix -7 floating pins

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@drjohnsmith Thanks for the feedback. The AR I referred to does cover the point you mentioned "in some packages, you have banks that have Power but NO IO pins" and does mention "(e.g., bank 13 does not exist, but Vcco pins do)?" in title. 

 

However I agree with you that seems the AR is not easily searchable and needs to be fixed. Will take your feedback and review the AR internally and update with keywords to make it more easily searchable. 

 

 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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Visitor vishwajit_01
Visitor
545 Views
Registered: ‎05-09-2018

Re: Artix -7 floating pins

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Thanks, but I didn't get the answer whether de-coupling capacitors are to be connected to those pins since they do not have I/O pins?

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Community Manager
Community Manager
539 Views
Registered: ‎07-23-2015

Re: Artix -7 floating pins

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@vishwajit_01 If you plan to migrate to higher density packages to use Bank 13, have decoupling caps along with a VCCO connection. If no plan, just connect it to other VCCO Power rail with no decaps. 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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