09-28-2018 12:16 AM
I have a strange behaviour in an Artix 7 design. Actually it is not my design and I am not an expert, so please excuse me. The design is basically an LVDS to USB converter. We have a strange bug which leads to some transmitted bytes (USB) being zero although they should not be and we did not find any bug in the code after 3 days of investigation. Our current guess is that it has something todo with the FIFOs used between the different clock domains.
However, the strange thing is, that the bug vanishes once the JTAG debugger is connected (physically and in the hardware manager), which makes debugging quite difficult. Once the debugger has been connected, it can be removed and the bug still does not appear. Only after a re-initialization of the FPGA it is back.
I do not want to go into the design itself as I am not an expert for FPGA stuff. I would like to know if someone experienced something similar or if someone can image what might be happening there. From my understanding, connecting the debugger should not change anything in the behaviour of the FPGA. Or did we miss something? Any help is welcome.
The device is an Artix 7 XC7A15T-2FGG484C on a custom board. Power supply seems to be ok.
09-28-2018 01:57 AM
thanks for the input.
I don't see how enabling the JTAG connection may reduce electro static problems, but I will have a look into that.
According to the guy who made the code, the timing contraint are well statisfied, even at double the frequency we are operating at. Also here, I don't see how enabling the JTAG connection may change the timings in the design.
09-28-2018 02:20 AM
Reconfirm, In the same FPGA ROM file, the error will disappear when JTAG is connected, and errors will appear when JTAG is not connected.I understand that, right?
If yes, how long does it take to make a mistake when JTAG is not connected?
09-28-2018 02:25 AM
Yes, it is the same bitstream, in both cases loaded from the flash. Just connecting the prommer and enabling the hardware manager makes the bug go away.
I just figured out something interesting, which might answer your question: I do measurements, which are initialized from the PC and the FPGA is responsible for taking the data from the LVDS lanes and transmit it to the PC. I saved the time between two errors and plotted the histogram of a lot of errors. It turns out that it always happens when I start a measurement at multiples of 2.75 seconds after the last error. So it seems like there is something happening every 2.75s which causes the bug. If I initate a measurement at that moment, it fails.
What is happening in the FPGA every 2.75 seconds that is disabled when I enable JTAG?
BTW: Disabling the JTAG in the FPGA did not solve the problem.
09-28-2018 02:36 AM
I think it's a matter of board. I suspect there is an interference signal with a period of 2.75 seconds.
You can test the voltage at the data transfer point to see if there is any difference between JTAG connection and JTAG without connection.
hope to help you.
09-28-2018 04:47 AM
I think we found the problem and a solution. I noticed that the FPGA is continously communicating with the flash, which should not be the case once it is initialized. It also had a period of 2.75 seconds, which was quite suspicious.
So the guy who wrote the FPGA code told me to try to set the option "Prohibit usage of the configuration pins as user I/O and persist after configuration" to NO. This option can be found in the advanced bistream settings.
Once this option was turned off, everything works fine.
Thank you very much anyway :)