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Explorer
Explorer
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Registered: ‎04-06-2017

Could the input pin of 7 series be floated?

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If one user IO is configured as input and is not pulled up or pulled down, can I leave it open? Will the IO circuit be damaged by the increasing current due to a voltage in the middle point of high level and low level? 

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: Could the input pin of 7 series be floated?

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floating a pin does not cause dammage by itself,

 

but if yo dirve it out of its operating bounds, it will get damaged.

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Explorer
Explorer
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Registered: ‎09-17-2018

Re: Could the input pin of 7 series be floated?

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No issue,

Xilinx IC designers are aware users sometimes do not take care in their designs, so all IO are designed to not suffer any cross-current damage (electromigration rules are followed to provide wider metal lines).  That said, good design practice wouls be to enable the weak pullup or pulldown on IO so that input pins do not float.  The extra current from floating inputs is not large, but does contribute to wasted power (less than ~ 1mA per input pin when at 1/2 Vcco).

Exceeding the values in Table 1 of the data sheet will result in damage, so always stay in the safe region, and stay below limits in Table 2 if you expect your design to actually work.

The final rules to observe are the ESD limits, and the Latch-Up current limits for IO (<100 mA forced into any IO pin or bank, <200 mA into all IO banks).

l.e.o.

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Scholar drjohnsmith
Scholar
657 Views
Registered: ‎07-09-2009

Re: Could the input pin of 7 series be floated?

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Good question,
Abs no problem leaving un used pins un constrained, I've doen it for decades, so has every one else I know,
BUT , dammed good question,
I seem to remember they are set default in the tools to weak pull up / weak hold, but for the life of me, I can not find where it says that.
Explorer
Explorer
592 Views
Registered: ‎07-17-2014

Re: Could the input pin of 7 series be floated?

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Just to chime in as an extra voice of reason - You should never do that. 

I've played with it for fun to see what happens and it's not good. All sorts of bizarre stuff goes on with busy FPGAs.

Unconnected I/O should have weak pull-up/down termination enabled by default.

As for any over/under-voltage transients that exceed protection -- that's already been mentioned. 

Community Manager
Community Manager
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Registered: ‎07-23-2015

Re: Could the input pin of 7 series be floated?

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@drjohnsmith wrote:
I seem to remember they are set default in the tools to weak pull up / weak hold, but for the life of me, I can not find where it says that.

Its in the bitsream setting for unused pins in the design. Below snippet from Page#293 of UG908 v2018.3 

unused_pin.JPG

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Explorer
Explorer
572 Views
Registered: ‎04-06-2017

Re: Could the input pin of 7 series be floated?

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If I define a pin as input, for example, system clk, I do not actually connect it with a clock source, but rather float this pin. This floated pin is not an unused pin. Will this cause damage?
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Explorer
Explorer
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Registered: ‎09-17-2018

Re: Could the input pin of 7 series be floated?

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No, it will not.

Damage occurs by exceeding values in Table 1 of the data sheet.

Or ESD.

Or latch-up (injecting > 100 Ma into a io or bank, > 200 ma to a device total of io)

l.e.o.

Scholar drjohnsmith
Scholar
553 Views
Registered: ‎07-09-2009

Re: Could the input pin of 7 series be floated?

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floating a pin does not cause dammage by itself,

 

but if yo dirve it out of its operating bounds, it will get damaged.

Explorer
Explorer
538 Views
Registered: ‎07-17-2014

Re: Could the input pin of 7 series be floated?

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@greatmaverick wrote:
If I define a pin as input, for example, system clk, I do not actually connect it with a clock source, but rather float this pin. This floated pin is not an unused pin. Will this cause damage?

Let's try saying this another way.

Yes -- you can configure as an input and leave disconnected -- but don't leave it floating. Configure the input with the weak pullup or pulldown.

This takes care of weird operation that might occur because it's floating and is experiening external influence.

But - now that it MIGHT be connected to a signal from outside - (like a user hookup on a connector) - make sure you protect the input from ESD that might occur during any connection events.

Explorer
Explorer
521 Views
Registered: ‎04-06-2017

Re: Could the input pin of 7 series be floated?

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Thank for all of the responses.

My FPGA user clk input pin is connected with a MCU. At powering up, the MCU IO is float, the clk input pin of FPGA may

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Explorer
Explorer
507 Views
Registered: ‎04-06-2017

Re: Could the input pin of 7 series be floated?

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Thank for all of the responses.

My FPGA user clk input pin is connected with a MCU. After powering up, the MCU IO connected with clk pin of FPGA is high impedance until external trigger happens, the clk input pin of FPGA is floated at this phase. If I use weak pull-up or down IO setting of FPGA, will it degrades the integrity of clk signal?
For another question, What is your method of ESD protection when plugging to a signal connector when power is on.
Thank you
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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: Could the input pin of 7 series be floated?

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New questions...
DO pull ups / downs degrade signals, only if you get the wrong value resistance. The built in pull ups on fpgas are designed to not cause degradation problems, but this is bot a xilinx question.

ESD protection, now thats a real big question, way outside the forums.
this might help,
https://www.xilinx.com/support/documentation/white_papers/wp433-Mitigating-ESD-EOS.pdf

but its a BIG subject.
e.g. I have designed for companies and in applications over the range of options of a) ESD does not exist to b) every IO must be through a isolated 'bridge'.
Your options are many