04-02-2019 09:25 PM
I'm planning to interface the HMCAD1511 (https://www.analog.com/media/en/technical-documentation/data-sheets/hmcad1511.pdf) to a Zynq-7020 (on a Zedboard) and would like some advice on how to best design the LVDS interface for my particular ADC.
The HMCAD1511 is capable of producing 1000 MSPS @ 8-bit samples, contains 4 ADCs which output data in 2 wire mode. In single channel mode (the mode I am interested in) all 4 ADCs sample the input signal and produce data across the 8 LVDS output channels. Here is a picture of the timing diagram:
The LCLK is the bitclock and the FCLK is the frame clock. The LCLK is a DDR clock. My goal is to sample at the full 1000 MSPS rate, according to the datasheet, FCLK = 125 Mhz. LCLK = (8-bit sample / 2 wire) * FCLK = 500 Mhz. Would the Zynq-7020 be sufficient to handle these rates?
I've gone over some XAPP notes and various forum posts, like XAPP524, and it seems using primitives over the SelectIO Interface Wizard IP is the way to go. I have a rough idea of what to do from this forum post: https://forums.xilinx.com/t5/7-Series-FPGAs/Can-I-use-SelectIO-to-read-serialized-LVDS-ADC/td-p/918670
In my situation, would following XAPP524 for a DDR interface be the best approach, or is there something simpler I could implement? Any suggestions on interface architecture would be greatly appriciated as this is the first time I have done anything like this. I'd like to get something work as soon as I can as time for this project is at a premium!
I appriciate any input!
04-03-2019 02:15 PM
For ADCs similar to this the xapp524 is very useful.
It is more aimed at 12/14/16 bit interfaces from an ADC Sent in DDR.
This ADC is slightly different because the samples are 8-bits wide.
So the way xapp524 works is that it first takes the data and uses the idelay to reposition the sample edge in the centre of the data eye.
Then it will sample the frame clock with the iserdes. There is logic in the xapp that will look at the data coming out of this frame clock deserializer. It then applies a bitslip to the frame clock and the data until it achieves data alignment by finding the frame clock pattern.
Your task will be that you need to modify this to work on 8 bits.
In terms of speed you have a 500Mhz lane clock this is easily accommodated by the BUFIO.
You can use the BUFIO/BUFR scheme in this case because you will have 8 data lanes (16 pins) and an LVDS IO for the frame clock and an LVDS input for the lclk, so it can be accommodated in a single IO bank.
The Lclk must come in on a clock capable IO in the bank
04-03-2019 06:47 PM
04-04-2019 12:36 AM
stepping through the sim and studying the XAPP would be useful.
I think you need to focus on modifying the frame detect logic.
It is not as straight forward as I describe. there is a risk of getting the same data out of the ISERDES twice during the training and this can cause issues with ever finding the correct frame.
I would suggest you read and understand exactly what the frame detect circuit is doing before you try to make it 8 bits instead of 12/14/16
04-04-2019 09:00 AM
I see, I was hoping this would be more straightforward. My goal right now is to get something out of my ADC as quickly as possible, it doesn't necessarily have to be correct.
My initial thought was that the Frame clock logic would work out of the box since 14, 16-bit versions use an 8-bit sync code (11110000). If I could have my ADC produce that, wouldn't it work without any modifications?
04-04-2019 07:29 PM
I've attached the code I used that worked for me. It's just a quick and dirty test. It uses an IBUFDS to bring the LVDS signals onto the chip and then ISERDES2 to output the desrialized data. I found it helpful to use the Wizard initially for the ISERDESE2 etc to find out what the proper parameters were.
We used the FMC connector on a Zedboard with an XM105 breakout. I think 500 MHz is way to fast for that to work. I'd suggest using a slower speed to at least get things working. I'm not even sure you can get all your LVDS pairs on compatible banks on that connector.
I instantiate the attached object in a higer level object that has state machines to do the bitslip etc:
ADC_LVDS_0 : ADC_LVDS port map ( rx_inclock_p => rx_inclock_p, rx_inclock_n => rx_inclock_n, rx_in_p => rx_in_p, rx_in_n => rx_in_n, io_reset => io_reset, rx_data_align => rx_data_align, pll_locked => pll_locked, rx_outclock => rx_outclock, rx_out => rx_out );
In my case, I had a 16-bit ADC and have to not only do bitslip but byte-swap to get everything aligned. Having 8-bit data will simplify that part of it.
On the other hand, you want to run at 500 MHz for the bitclock. I only ran at 160 MHz (320 Mbit/sec) and got away, at least temporarily, with being a bit lazy on things like dynamic phase alignment to center the clock on the data (or the data on the clock). You have 2 ns. Look at Table 15 in the Artix 7 datasheet (which is what the Zynq fabric is):
If I understand the above correctly, you need the fastest speed grade (which I don't believe is what the Zedboard uses). You need to set the min/max input delay in your constraint file. Looking at the HMCAD1511 datasheet, you are going to have an extremely tight timing budget.
There are several people far more knowledgeable than myself that can hopefully provide better guidance. I basically did what others told me since I'm new to Vivado.
I prefer using a test pattern for bit-slip instead of the frame clock. The advantage of the test pattern is it lets you do delay on a per channel basis and lets you confirm that all the channels are functional. We don't even connect the frame clock on our boards since it just wastes scarce resouces and board space.
Again, I got it working, but I'm hardly an expert in these matters so hopefully I'm not leading you astray.
04-04-2019 08:27 PM - edited 04-04-2019 08:38 PM
Thanks for the great response. You're right, the zedboard won't be able to handle the 500Mhz bit clock of the HMCAD1511, but it is more of a proof of concept for future designs. We were able to fit all the necessary data and clock pins on I/O bank 35, so that shouldn't be a problem
I see you are using a PLL block to adjust the phase of the incoming bitclock. Would you be willing to share that code as well? Or if you have some barebone project with all the components and state machine I could look at, I'd be very grateful.
Could you also explain how you handled the io_reset for the code you provided (and possibly how you handled it for the SelectIO Wizard as well)?
For my current situation, I think reworking xapp524 may be more work than my deadline will permit, I'd rather get something simple working and tweak from there.
04-05-2019 12:45 AM