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Newbie tom.he
Newbie
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Registered: ‎01-11-2019

HR/HP IOB output jitter

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I am learning Xilinx Artix 7 family DC datasheet. and couldn't find the number of FPGA output, specially the difference between HR and HP pins, single-end and LVDS, and so on.

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439 Views
Registered: ‎01-22-2015

Re: HR/HP IOB output jitter

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@tom.he

I understand that you plan to generate a clock with the Artix-7 CMT and send it out an IO pin of the FPGA. If so, then jitter on this clock will be mostly determined by the jitter of the CMT clock generator.  As @tenzinc suggests, it is best to get this jitter number from the Vivado tools.

The CMT clock generator is configured using Vivado, where you select the “IP Catalog” and find the Xilinx Intellectual Property (IP) component that tenzinc mentioned called the “Clocking Wizard”. This wizard allows you to configure the CMT by specifying things like input clock frequency, input clock jitter, and desired output clock frequency. Based on your inputs, the Clocking Wizard will (on the Summary tab) show you the expected jitter for the output clock.

Mark
Clk_Wiz_6p0.jpg

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Registered: ‎01-22-2015

Re: HR/HP IOB output jitter

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@tom.he

Welcome to the Xilinx Forum!

Yes, there is lots to learn when starting out with FPGAs.

The Artix-7 belongs to a group of FPGAs that Xilinx calls the "7-Series".  Other FPGAs in this group are the Spartan-7, Kintex-7, and Virtex-7.  Much of the Xilinx documentation for the Artix-7 will start with the words "7 Series".

The Artix-7 has several different packages. Tables 4 and 5 in Xilinx document DS180 list the number of IO (HR and HP) and number of internal resources (eg. logic cells and RAM) associated with each package.

From DS180, you can then read Xilinx document UG471 to learn about the differences between HR and HP IO. There, you will also find that FPGA IO can be configured to be compatible with many different digital standards (eg. LVDS, LVTTL, and LVCMOS).

The title of your post mentions jitter. Jitter is mostly determined by the digital clocks that the FPGA can create for you using Clock Management Tiles (CMTs).  You can read about Artix-7 CMTs and jitter in Xilinx document UG472.

I’m sure you’ll have more questions. Don’t hesitate to ask.

Cheers,
Mark

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Newbie tom.he
Newbie
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Registered: ‎01-11-2019

Re: HR/HP IOB output jitter

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Hi Mark,

Thank you for your response.

Sorry, didn't describe my question clearly. I am trying to figure out Xilinx  FPGA Artix 7 series family IOB output jitters, in term of IOB types, and IOB banks. Somehow I can't find the number in the DC datasheet.  In example, for a Altera FPGA, I can find a number of the jitter for clock output on a regular I/O Pin: if the frequency is faster than 100MHz, the maximum jitter will be 650ps. Could you please tell me where I can find this kind of number in Xilinx DC datasheet?

 

Thanks,

-Tom

 

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Moderator
Moderator
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Registered: ‎09-18-2014

Re: HR/HP IOB output jitter

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Tom.he,

Similar to the note 3 on the PLL and MMCM output jitter spec states values will be available in the clocking wizard IP. Output jitter will vary depending on multiple factors which the vivado timing software/tools takes as input to give you an estimated output jitter figure. Recommend viewing UG949, Design Creation section. 

Regards,
T

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440 Views
Registered: ‎01-22-2015

Re: HR/HP IOB output jitter

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@tom.he

I understand that you plan to generate a clock with the Artix-7 CMT and send it out an IO pin of the FPGA. If so, then jitter on this clock will be mostly determined by the jitter of the CMT clock generator.  As @tenzinc suggests, it is best to get this jitter number from the Vivado tools.

The CMT clock generator is configured using Vivado, where you select the “IP Catalog” and find the Xilinx Intellectual Property (IP) component that tenzinc mentioned called the “Clocking Wizard”. This wizard allows you to configure the CMT by specifying things like input clock frequency, input clock jitter, and desired output clock frequency. Based on your inputs, the Clocking Wizard will (on the Summary tab) show you the expected jitter for the output clock.

Mark
Clk_Wiz_6p0.jpg

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Newbie tom.he
Newbie
432 Views
Registered: ‎01-11-2019

Re: HR/HP IOB output jitter

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Thanks Mark.

In your case, CMT can report the jitter value if a output clock is driven to a IOB. But I would like to understand the regular logic signal output's jitter from a FPGA PIN.

I agree that from clock uncertainty to register uncertainty can be reported by the tools. But I think IOB itself jitter shall be listed in the datasheet(s), and I couldn't find the number.

Regards,

-Tom

 

 

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335 Views
Registered: ‎01-22-2015

Re: HR/HP IOB output jitter

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Hi Tom,

        But I think IOB itself jitter shall be listed in the datasheet(s),
I think you’re referring to what Xilinx calls “System Jitter” (ref. UG903, pg98), which will depend on several factors (eg. clock frequency, output type and slew) for the IOB. I have not seen numbers for IOB system jitter listed in the Xilinx documentation. However, system jitter is part of the clock uncertainty data that Vivado uses for timing analysis. As with numbers for CMT clock jitter, you can use the Vivado tools to see numbers for system jitter. Specifically, the timing path summary header in the report_timing text report (ref. UG906, Figure 5-6) shows “Total System Jitter”.

Mark

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