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Adventurer
Adventurer
651 Views
Registered: ‎10-28-2018

How to parse LVDS differential input signal to a differential output?

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Hi

 

  How to parse LVDS differential input signal to a differential output in terms of verilog code? 

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1 Solution

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Explorer
Explorer
560 Views
Registered: ‎07-17-2014

Re: How to parse LVDS differential input signal to a differential output?

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More like:

// a general idea - might have syntax errors
// see ug953 for more info.
//

module myTest (
    input wire RX0_P,
    input wire RX0_N,
    output wire TX0_P,
    output wire TX0_N,
);

wire  rx0;

IBUFDS ibuf_rx0 (
   .I   (RX0_P),
   .I_B (RX0_P),
   .O   (rx0)
);

OBUFDS obuf_tx0 (
   .I    (rx0),
   .O    (TX0_P),
   .O_B  (TX0_N)
);

endmodule

 

 


sort of. They should still be defined as LVDS... but you can use an IBUFDS to from differential to single ended and then wire them directly to an OBUFDS.

You should really download the Series 7 Libraries and the SelectIO userguides.

And keep in mind, in the simplest form above, you may introduce delay artifacts that have to be compensated for.

You haven't really supplied a lot of information about the video source or receiver. So -- all this is dependant on testing.


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10 Replies
Explorer
Explorer
605 Views
Registered: ‎07-17-2014

Re: How to parse LVDS differential input signal to a differential output?

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Could you be more specific? (BTW, there are a lot of fun LVDS Xappnotes available)

Next - download the SelectIO user guide and the series 7 libraries userguide.

You will want to look up 
IDELAY and ODELAY
ISERDES and OSERDES

Are you asking how to look at the data?

Without more info --

Getting the data IN:
 Configure your input ports for LVDS Input and connect that to the input of an ISERDES unit (optionally through an IDELAY unit).
 You haven't mentioned how clocking is supplied and that needs to be considered -- so make sure to check Xappnotes for LVDS examples to see how to deal with clocking.

Getting the data OUT: 
  Connect your parallel data stream (and clocking) to an OSERDES unit (optionally through an ODELAY unit if you need it) to a IOpad configured for LVDS output.

And there ya go.

I know -- not a lot of detail -- but you need to supply us with detail for us to do the same in return.

Cheers,

 -Ben

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Adventurer
Adventurer
588 Views
Registered: ‎10-28-2018

Re: How to parse LVDS differential input signal to a differential output?

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Hi Ben,

  Thanks for the response. Here are more details of my project. 

On the hardware (PCB), I have these LVDS signals coming into the FPGA (Spartan 7) which are physically connected to these IOs (bank34) of the FPGA: 

RX0_P, RX0_N connected to IO_L8P_T1_34 and IO_L8N_T1_34

RX1_P, RX1_N connected to IO_L10P_T1_34 and IO_L10N_T1_34

RX2_P, RX2_N connected to IO_L1P_T1_34 and IO_L1N_T1_34

RX3_P, RX3_N connected to IO_L7P_T1_34 and IO_L7N_T1_34

CLK_P, CLK_N connected to IO_L12P_T1_MRCC_34 and IO_L12N_T1_MRCC_34

 Without making any modifications to the LVDS signals, how do I parse the signal into another set of FPGA IOs in bank14 ? 

RX0_P, RX0_N signal to IO_L8P_T1_ D11_14 and IO_L8N_T1_ D12_14

RX1_P, RX1_N signal to IO_L10P_T1_ D14_14 and IO_L10N_T1_ D15_14

RX2_P, RX2_N signal to IO_L7P_T1_ D09_14 and IO_L7N_T1_ D10_14

RX3_P, RX3_N signal to IO_L13P_T2_ MRCC_14 and IO_L13N_T2_ MRCC_14

CLK_P, CLK_N signal to IO_L12P_T1_ MRCC_14 and IO_L12N_T1_ MRCC_14

   On the PCB, these bank14 IOs are connected to the LCD screen connector. 

Basically, I just want to wire the incoming LVDS signals in bank34 to the output IOs in bank14. 

 

Thanks!

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Explorer
Explorer
569 Views
Registered: ‎07-17-2014

Re: How to parse LVDS differential input signal to a differential output?

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@vivienwwp wrote:

Hi Ben,

  Thanks for the response. Here are more details of my project. 

On the hardware (PCB), I have these LVDS signals coming into the FPGA (Spartan 7) which are physically connected to these IOs (bank34) of the FPGA: 

RX0_P, RX0_N connected to IO_L8P_T1_34 and IO_L8N_T1_34

RX1_P, RX1_N connected to IO_L10P_T1_34 and IO_L10N_T1_34

RX2_P, RX2_N connected to IO_L1P_T1_34 and IO_L1N_T1_34

RX3_P, RX3_N connected to IO_L7P_T1_34 and IO_L7N_T1_34

CLK_P, CLK_N connected to IO_L12P_T1_MRCC_34 and IO_L12N_T1_MRCC_34

 Without making any modifications to the LVDS signals, how do I parse the signal into another set of FPGA IOs in bank14 ? 

RX0_P, RX0_N signal to IO_L8P_T1_ D11_14 and IO_L8N_T1_ D12_14

RX1_P, RX1_N signal to IO_L10P_T1_ D14_14 and IO_L10N_T1_ D15_14

RX2_P, RX2_N signal to IO_L7P_T1_ D09_14 and IO_L7N_T1_ D10_14

RX3_P, RX3_N signal to IO_L13P_T2_ MRCC_14 and IO_L13N_T2_ MRCC_14

CLK_P, CLK_N signal to IO_L12P_T1_ MRCC_14 and IO_L12N_T1_ MRCC_14

   On the PCB, these bank14 IOs are connected to the LCD screen connector. 

Basically, I just want to wire the incoming LVDS signals in bank34 to the output IOs in bank14. 

If you're just making a repeater, you just wire the inputs to the outputs.

You'd probably be better off keeping all inputs and outputs on the same I/O bank for minimum and constrainable latency.

 

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Adventurer
Adventurer
564 Views
Registered: ‎10-28-2018

Re: How to parse LVDS differential input signal to a differential output?

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Hi Ben

  Do you mean not defining these IOs as differential but just regular IO LVCMOS25? 

   just do this:

module myTest(

input wire RX0_P

input wire RX0_N

output wire TX0_P

output wire TX0_N

);

  assign TX0_P = RX0_P;

  assign TX0_N = RX0_N;

endmodule

 

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Explorer
Explorer
561 Views
Registered: ‎07-17-2014

Re: How to parse LVDS differential input signal to a differential output?

Jump to solution

More like:

// a general idea - might have syntax errors
// see ug953 for more info.
//

module myTest (
    input wire RX0_P,
    input wire RX0_N,
    output wire TX0_P,
    output wire TX0_N,
);

wire  rx0;

IBUFDS ibuf_rx0 (
   .I   (RX0_P),
   .I_B (RX0_P),
   .O   (rx0)
);

OBUFDS obuf_tx0 (
   .I    (rx0),
   .O    (TX0_P),
   .O_B  (TX0_N)
);

endmodule

 

 


sort of. They should still be defined as LVDS... but you can use an IBUFDS to from differential to single ended and then wire them directly to an OBUFDS.

You should really download the Series 7 Libraries and the SelectIO userguides.

And keep in mind, in the simplest form above, you may introduce delay artifacts that have to be compensated for.

You haven't really supplied a lot of information about the video source or receiver. So -- all this is dependant on testing.


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Adventurer
Adventurer
547 Views
Registered: ‎10-28-2018

Re: How to parse LVDS differential input signal to a differential output?

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Thanks Ben! I'll try it out soon on Vivado and see if it works. 

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Adventurer
Adventurer
514 Views
Registered: ‎10-28-2018

Re: How to parse LVDS differential input signal to a differential output?

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Hi Ben

   I have used your recommendation and I get this. Capture.PNG

 

 

 

 

 

 

 

 

 

 

 

I was just wondering how different is using IBUFDS and OBUFDS to using a IBUFDS_DIFF_OUT ? 

In IBUFDS_DIFF_OUT , can the O and OB outputs be connected to a top level port in the design or is it only a buffer internally? 

Thanks

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Adventurer
Adventurer
505 Views
Registered: ‎10-28-2018

Re: How to parse LVDS differential input signal to a differential output?

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By the way, I ran a behavioural simulation and I get the expected waveform.

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Explorer
Explorer
497 Views
Registered: ‎07-17-2014

Re: How to parse LVDS differential input signal to a differential output?

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@vivienwwp wrote:

Hi Ben

   I have used your recommendation and I get this. Capture.PNG

 

 

 

 

 

 

 

 

 

 

 

I was just wondering how different is using IBUFDS and OBUFDS to using a IBUFDS_DIFF_OUT ? 

In IBUFDS_DIFF_OUT , can the O and OB outputs be connected to a top level port in the design or is it only a buffer internally? 

Well, the I and O prefix are input|output respectively. Both use single ended signals internally.
The IBUFDS_DIFF_OUT give the designer internally inverted signals in case the design needs it for something.

Technically, you could use an IBUFDS_DIFF_OUT in your schematic above, but the .OB port isn't needed for the OBUFDS... but maybe you could connect it elsewhere for some other design need..

 

Adventurer
Adventurer
441 Views
Registered: ‎10-28-2018

Re: How to parse LVDS differential input signal to a differential output?

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Hi Ben

  I finally had the hardware to test the code. The repeater code didn't work at all.

The IBUFDS and OBUFDS design yielded some results but not great. The LCD screen was showing distorted lines. 

   The design is exactly as shown in the schematic. What do you think is the problem? Do you i need to set DIFF_TERM to true? I do not have 100 ohm termination between P and N at the inputs on the physical board. I also do not have 100 ohm termination between P and N at the outputs. 

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