UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
3,140 Views
Registered: ‎02-04-2013

ISERDES - MMCM Dynamic phase shift

Hello everybody,

 

I am using Artix7 and I would like to read data from serializer IC (FIN210AC in my case) using two LVDS signals only - without the clock from the serializer IC (please see the attached image). I thought i could dynamically shift the CKSI clock phase to match the DSO. Can this be done? 

 

So i should somehow limit the range of the phase shift to match the particular bit at ISERDES. Is this the way it should be done?

 

Regards

Klemen

sch.jpg
0 Kudos
2 Replies
Moderator
Moderator
3,097 Views
Registered: ‎02-16-2010

Re: ISERDES - MMCM Dynamic phase shift

If both FPGA and serializer are clocked using the same source, then you can adjust the phase of the clock driving the ISERDES of FPGA using IDELAY primitive.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
3,080 Views
Registered: ‎02-04-2013

Re: ISERDES - MMCM Dynamic phase shift

The clock source is the same. The clock source generates strobe signal at the serializer.

 

Do you mean i should set it to fixed delay and experiment with the tap value or should i set it to dynamic - but in this case i will not know whether it was tuned to bit0 or not?

 

The strobe to bit0 delay is, for instance, at 20MHz: 77ns - 90,5ns. This is quite large compared to ps range delay for each tap.

 

Regards

Klemen

 

0 Kudos