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Visitor raychng
Visitor
4,946 Views
Registered: ‎07-19-2015

LCD counter implementation on KC705 evaluation board help

Hi all,

 

  I am facing problems trying to implement an LCD counter onto my Kintex 705 evaluation board. I am not able to show up anything on the LCD counter even though there are no errors. Here are the warnings I encounted in the process.  However, I think the problem could be with my timing constraints. I will greatly appreciate if anyone can help me with it, I really am stuck with this. I have attached my source code and the constraints file. Thanks. 

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LCD counter warnings.png
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5 Replies
Xilinx Employee
Xilinx Employee
4,940 Views
Registered: ‎08-01-2008

Re: LCD counter implementation on KC705 evaluation board help

I would prefer you to run the simulation
check this document

http://www.ece.gatech.edu/academic/courses/fpga/Xilinx/downloads/lab3.pdf
Thanks and Regards
Balkrishan
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Voyager
Voyager
4,917 Views
Registered: ‎04-21-2014

Re: LCD counter implementation on KC705 evaluation board help

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FbzrObqlUrycrqZrBaGuvfYno is
end FbzrObqlUrycrqZrBaGuvfYno;
architecture tb of FbzrObqlUrycrqZrBaGuvfYno is
  component lcd is
   port(
     iCLK_p    : IN  std_logic;
     iCLK_n    : IN  std_logic;
     iRST      : IN  std_logic;
     oSF_D     : OUT std_logic_vector(11 downto 8);
     oLCD_E    : OUT std_logic;
     oLCD_RS   : OUT std_logic;
     oLCD_RW   : OUT std_logic
   );
  end component lcd;
  signal RST   : std_logic := '1';
  signal clk   : std_logic := '0';
  signal clk_p : std_logic;
  signal clk_n : std_logic;
begin

  clk   <= not clk after 5 nS;
  RST   <= '1', '0' after 100 nS;
  clk_p <= clk;
  clk_n <= not clk;

  lcd_U1 : lcd
  port map(
    iCLK_p    => clk_p,
    iCLK_n    => clk_n,
    iRST      => RST,
    oSF_D     => open,
    oLCD_E    => open,
    oLCD_RS   => open,
    oLCD_RW   => open
  );

end architecture tb;

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Visitor raychng
Visitor
4,821 Views
Registered: ‎07-19-2015

Re: LCD counter implementation on KC705 evaluation board help

@morgan198510 @balkris Thanks for the advice, apologies for the wait. I have added a testbench using the code by @morgan198510 . However, I now faced another problem, I can't seem to run a behavioural simulation. The "Simulation Running" windows pops up but then immediately closes. There are no error or warning messages. Synthesis and implementation still runs fine.

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Visitor raychng
Visitor
4,818 Views
Registered: ‎07-19-2015

Re: LCD counter implementation on KC705 evaluation board help

@morgan198510@balkris Sorry, I managed to solve the issue. So, after I run a simulation what should I do to find out whats the problem with my code?

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Voyager
Voyager
4,800 Views
Registered: ‎04-21-2014

Re: LCD counter implementation on KC705 evaluation board help


@raychng wrote:

@morgan198510@balkris Sorry, I managed to solve the issue. So, after I run a simulation what should I do to find out whats the problem with my code?


I'm glad you got the basic testbench up and running.  Hope it helps.  As for what you should do, try this:

 

Compare your actual outputs to your expectations.  If they don't match, add the internal signals to your waveform and repeat.  Divide and conquer. 

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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