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Participant kbj1213
Participant
304 Views
Registered: ‎08-25-2015

LVDS I/O standard on an FPGA

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Hi, I'm a beginner for designing a digital system on FPGA.

 

I'm reading a datasheet regarding with I/O standard(ug-471) and user guide regarding with my FPGA (ug-810).

 

I have a question about a voltage of I/O.

 

In ug-471, the table on image tells that LVDS I/O std requires 1.8V both for input and output.

So, I think I should set all of input and output pins which has "LVDS" as I/O standard.

 

But it's confusing for me that there are lots of pins which have LVDS I/O standard but are on the Bank of VDD more than 1.8V.

(for example, AD28 pin on the pictures which I upload)

 

How should I set this pin when synthesizing?

LVDS ? or LVCMOS25 ? for LVCMOS18 ?

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Xilinx Employee
Xilinx Employee
302 Views
Registered: ‎08-10-2008

回复: LVDS I/O standard on an FPGA

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Hi,

LVDS input pair does not necessarily require a VCCO of 1.8V, unless you use the DIFF_TERM termination.

Read 'Rules for Combining I/O Standards in the Same Bank' in UG471 and read Note1 after Table 1-55.

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3 Replies
Xilinx Employee
Xilinx Employee
303 Views
Registered: ‎08-10-2008

回复: LVDS I/O standard on an FPGA

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Hi,

LVDS input pair does not necessarily require a VCCO of 1.8V, unless you use the DIFF_TERM termination.

Read 'Rules for Combining I/O Standards in the Same Bank' in UG471 and read Note1 after Table 1-55.

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Scholar u4223374
Scholar
265 Views
Registered: ‎04-26-2015

Re: LVDS I/O standard on an FPGA

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@kbj1213  You shouldn't be able to actually select the "LVDS" IO standard for any of those pins, because they're all on a HR bank ("LVDS" is only available on the HP banks). Instead you can select "LVDS_25", which is only available on the HR banks and (as the name suggests) works just fine at 2.5V.

 

What @iguo has said is relevant to running the HR banks at 3.3V. In this case you can still use the LVDS_25 standard, but the internal LVDS termination will be disabled - external termination must be provided. Since the closest you can get the external termination is normally about 10cm (unless you're designing a custom board) this is less than ideal.

Xilinx Employee
Xilinx Employee
240 Views
Registered: ‎08-10-2008

Re: LVDS I/O standard on an FPGA

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Yes I did not distinguish LVDS and LVDS_25 here, just want to say the LVDS/_25 input standard voltage does not have to be same with Vcco.
@u4223374 is correct. LVDS in HP while LVDS_25 in HR.
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