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Visitor svenkesd
Visitor
1,058 Views
Registered: ‎10-02-2018

LVDS clock input for Spartan 7

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I am attempting to use a LMK61E2 clock source in LVDS mode to generate a clock for a Spartan 7 xc7s25ftgb196-2. 

 

When I scope the signal lines with a high speed probe, the LVDS waveform is present while the FPGA is in process of being configured (although somewhat distorted due to lack of proper termination), but the lines are grounded after configuration is done.  Am I doing something wrong in configuration that causes these pins to ground the clock signals?  I can't get anything to run from this clock internally in the FPGA either.

 

FYI the HR Bank for the input pins VCCO is 2.5V, there is no external LVDS termination on the PCB.

 

Here is my relevant .xdc:

 

set_property PACKAGE_PIN M2 [get_ports CLK_SAMPLING_N]
set_property IOSTANDARD LVDS_25 [get_ports CLK_SAMPLING_N]
set_property DIFF_TERM TRUE [get_ports CLK_SAMPLING_N]

set_property PACKAGE_PIN M3 [get_ports CLK_SAMPLING_P]
set_property IOSTANDARD LVDS_25 [get_ports CLK_SAMPLING_P]
set_property DIFF_TERM TRUE [get_ports CLK_SAMPLING_P]

 

And here is where I try to connect it to an input buffer in my top level VHDL:

 

CLK_SAMPLING_P      : in    std_logic;
CLK_SAMPLING_N      : in    std_logic;

 

SAMPLING_IBUFDS : IBUFGDS
generic map (
    DIFF_TERM    => TRUE,
    IBUF_LOW_PWR => FALSE,
    IOSTANDARD => "DEFAULT"
    )
port map (
    O => clk_sample,
    I => CLK_SAMPLING_P,
    IB => CLK_SAMPLING_N
    );

 

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1 Solution

Accepted Solutions
989 Views
Registered: ‎01-22-2015

Re: LVDS clock input for Spartan 7

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@svenkesd

 

-some things to try:

1) Use IBUFDS instead of IBUFGDS. Note that UG953 does not show IBUFGDS as a valid primitive for 7-Series devices.

 

2) The package file for the xc7s25ftgb196 shows that one of your clock pins (M2) can also be used as a VREF input for bank 34. Try using the following XDC constraint to indicate that VREF for bank 34 is to be generated internally to the FGPA. 

set_property INTERNAL_VREF 0.75 [get_iobanks 34]

 

Mark

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6 Replies
Scholar drjohnsmith
Scholar
1,019 Views
Registered: ‎07-09-2009

Re: LVDS clock input for Spartan 7

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does it simulate

 

what warnings are you getting in synthesis  P&R

 

what voltage is the clock when the fpga is configuring 

 

The LMK61E2  is a 3v3 part, and your using a 2v5 lvds standard in the fpga,

    are you AC coupling the clock in to the fpga ?

 

Have you seen this

 

https://www.xilinx.com/support/answers/43989.html

 

Visitor svenkesd
Visitor
1,006 Views
Registered: ‎10-02-2018

Re: LVDS clock input for Spartan 7

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Thank you for answering. 

 

The clock voltage is about 1.3V common mode, and 500mV differential when the FPGA is configuring.  I think this should match the capabilities of a LVDS_25 port, from page 11 of DS189.  There is no AC coupling as I had thought the voltages were compatible, but maybe I am wrong.

 

lvds_25.png

 

I am working on trying a simulation.  Is a behavioral simulation the best test for this? Or post-synthesis, or post-implementation simulation?

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990 Views
Registered: ‎01-22-2015

Re: LVDS clock input for Spartan 7

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@svenkesd

 

-some things to try:

1) Use IBUFDS instead of IBUFGDS. Note that UG953 does not show IBUFGDS as a valid primitive for 7-Series devices.

 

2) The package file for the xc7s25ftgb196 shows that one of your clock pins (M2) can also be used as a VREF input for bank 34. Try using the following XDC constraint to indicate that VREF for bank 34 is to be generated internally to the FGPA. 

set_property INTERNAL_VREF 0.75 [get_iobanks 34]

 

Mark

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Scholar drjohnsmith
Scholar
967 Views
Registered: ‎07-09-2009

Re: LVDS clock input for Spartan 7

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Simulation

 

always start with the simplest, the behavioral.

   if that does not work then the others wont...

 

 

AC coupling LVDS clocks, in my experience,  ALWAYS a good idea,  

 

I have not things to hand, but suggest as an example, run  the IO wizard, and make a lvds input.

    select external lvds clock ,

 

then have a look at what has been created and the constraints as a template.

 

 

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Visitor svenkesd
Visitor
955 Views
Registered: ‎10-02-2018

Re: LVDS clock input for Spartan 7

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This appears to have done it, thank you!

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948 Views
Registered: ‎01-22-2015

Re: LVDS clock input for Spartan 7

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@svenkesd

 

You are welcome!

It would be very helpful if you identified which one of the suggestions made things work.  -or did you need them both?

 

Thanks,

Mark

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