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Observer rishubnagpal
Observer
170 Views
Registered: ‎04-19-2018

Maximum LVDS clock input for Zynq

Hi,

I'd like to interface an 8-bit, 1GSPS, ADC with a Zedboard which has a Zynq-7020 chip. The bit clock is double data rate so it'll be clocked at 4Ghz and the frame clock is 1Ghz. The clocks and data bus will be passed to the Zynq via an FMC connector (LVDS)

Would the Zynq be able to handle these data and clock rates?

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2 Replies
Voyager
Voyager
128 Views
Registered: ‎02-01-2013

Re: Maximum LVDS clock input for Zynq

 

That's too fast for Zynq SelectIO interfaces. They top-out at or below ~1 GHz.

2019-02-17_19-55-22.jpg

-Joe G.

 

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Observer rishubnagpal
Observer
119 Views
Registered: ‎04-19-2018

Re: Maximum LVDS clock input for Zynq

Hi @jg_bds,

Thanks for the quick response - I just reviewed my ADC's datasheet and it appears I made an error - the data is sent across 8 channels. In my original calculations, I had assumed it was a single channel output. This changes the frame clock to 125Mhz and the bitclock to 500Mhz. From the chart you posted, it looks like the Zynq-7020 will be able to handle it.

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