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Visitor cecillove
Registered: ‎09-27-2012

Optional Output Register Clock on Series 7 BlockRAM primitive

We are trying to use the optional output register on series 7 block RAM.

In the series 7 memory resources user guide, we see the optional output register documented (figure 1-5)

but we don't see the port for the independent output register clock in the portname and description table.

Is the output clock available as an independent connection on the block ram primitive?

Which pin?


The documentation says this:

Optional Output Registers
The optional output registers improve design performance by eliminating routing delay to
the CLB flip-flops for pipelined operation. An independent clock and clock enable input is
provided for these output registers. As a result the output data registers hold the value
independent of the input register operation. Figure 1-5 shows the optional output register.


Which pin on the blockram primitive is this independent clock? I see the independent clock enable REGCEB etc.



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1 Reply
Registered: ‎01-23-2009

Re: Optional Output Register Clock on Series 7 BlockRAM primitive

This paragraph in the User Guide is wrong. There is an independent clock enable for the optional registers, but it shares the same clock as the rest of the features on that port. If you look at the diagram immediately below that paragraph, it shows the optional output registers as being clocked by the same clock that are used for the address bits.



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