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7,598 Views
Registered: ‎10-23-2013

Place:1198-Error : Route cause and possible solution

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Hello everyone,

 

I testes my FPGA-Design on an evaluation board (Spartan 6 - LX9) before implementing (VHDL with ISE 14.6) the software on the destination device (Spartan 6 - LX45). One error occurs in the course of this transition:

 

--------------------------------------------------------------------------------------------------------------------------------------------

ERROR:Place:1198 - A PLL clock component is not placed at a routable site. The
   PLL component <CLOCK/pll_base_inst/PLL_ADV> is placed at site <PLL_ADV_X0Y1>.
   The corresponding clock load component <top_out_VIDEO_Clock> is placed at
   site <PAD215>. The PLL can use the fast path between the PLL and the clock
   load if they are placed in adjacent horizontal clock regions. You may want to
   analyze why this problem exists and correct it. This placement is UNROUTABLE
   in PAR and therefore, this error condition should be fixed in your design.
   You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote
   this message to a WARNING in order to generate an NCD file. This NCD file can
   then be used in FPGA Editor to debug the problem. A list of all the COMP.PINS
   used in this clock placement rule is listed below. These examples can be used
   directly in the .ucf file to demote this ERROR to a WARNING.
   < PIN "CLOCK/pll_base_inst/PLL_ADV.CLKOUT0" CLOCK_DEDICATED_ROUTE = FALSE; >
   < NET "top_out_VIDEO_Clock" CLOCK_DEDICATED_ROUTE = FALSE; >


ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

--------------------------------------------------------------------------------------------------------------------------------------------

 

 

The sugested solution (insert NET "top_out_VIDEO_Clock" CLOCK_DEDICATED_ROUTE = FALSE; to ucf-file) works.

 

But I want to understand the route cause of this error. After that there might be a better solution, leading to neither error nor warning. Or I can prevent this errors in the future.

 

Here are some more information: The clock-input (leading to the PLL-instance from XILINX ipCore-Generator) is on Pin L15 (Bank 1, IO_L42P_GCLK7_M1UDM_1), the video-clock-output is on Pin U8 Bank 2, IO_L41P_2). Is the crossing between Bank 1 and 2 the problem?

 

Thank you for your help!

 

 

 

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1 Solution

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4,944 Views
Registered: ‎10-23-2013

Re: Place:1198-Error : Route cause and possible solution

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I didn't need to insert an OBUF, but in the PLL instance I needed an BUFG and in the Video-instace an ODDR2.

 

Now everything works fine.

 

  ODDR2_CLK : ODDR2
  generic map(
    DDR_ALIGNMENT => "C0",               -- Sets output alignment to "NONE", "C0", "C1" : as D0 and D1 are constant the allignment does not matter here!
    INIT          => '0', -- Sets initial state of the Q output to '0' or '1'
    SRTYPE        => "ASYNC")             -- Specifies "SYNC" or "ASYNC" set/reset
  port map (
    Q             => out_VIDEO_Clock,   -- 1-bit output data
    C0            => i_CLOCK_VideoClock,   -- 1-bit clock input
    C1            => int_s_VideoClock_n, -- 1-bit clock input
    CE            => '1',  -- 1-bit clock enable input
    D0            => '1',     -- 1-bit data input (associated with C0)
    D1            => '0',     -- 1-bit data input (associated with C1)
    R             => '0',     -- 1-bit reset input
    S             => '0'      -- 1-bit set input
  );

 

 

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11 Replies
Xilinx Employee
Xilinx Employee
7,593 Views
Registered: ‎04-16-2012

Re: Place:1198-Error : Route cause and possible solution

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Hi,

 

This error is caused due to the PLL loads. The loads of the PLL should be placed in the horizontal clock region as mentioned in the error message. So try placing the loads in the horizontal clock region.

 

Thanks

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7,582 Views
Registered: ‎10-23-2013

Re: Place:1198-Error : Route cause and possible solution

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wrote: "The loads of the PLL should be placed in the horizontal clock region"

 

 

Two questions regarding this advice?:

 

1) "loads of the PLL" are the output signals of the PLL, routed to i.e. the video-clock-pin?

 

2) I do not know what you mean by "horizontal clock region"?

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Xilinx Employee
Xilinx Employee
7,570 Views
Registered: ‎04-16-2012

Re: Place:1198-Error : Route cause and possible solution

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Hi,

1. Remove LOC constraints on the video-clock pin (output of PLL), the tool will LOC the pin to the correct location.
2. See page no. 14 of ug382.

Thanks
--------------------------------------------------------------------------------------------
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7,566 Views
Registered: ‎10-23-2013

Re: Place:1198-Error : Route cause and possible solution

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wrote: "Remove LOC constraints on the video-clock pin (output of PLL), the tool will LOC the pin to the correct location."

 

Do you suggest to route the signal to another output pin or is "Remove LOC constraints" some sort of configuration I'm not yet aware of?

 

The output pin of the video-clock is fixed due to my hardware. Therefore the clock signal MUST finally be routed to this pin. If I could make a redesign of my pcb, i could consider this restrictions (after fully understanding them). But now the input and output pins are fixed due to the hardware.

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Xilinx Employee
Xilinx Employee
7,562 Views
Registered: ‎04-16-2012

Re: Place:1198-Error : Route cause and possible solution

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Hi,

Since your hardware pinout is fixed, I suggest you to use BUFG on the output net of PLL.

Thanks
--------------------------------------------------------------------------------------------
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7,559 Views
Registered: ‎10-23-2013

Re: Place:1198-Error : Route cause and possible solution

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Insertion of a BUFG in the PLL-instance (selecting the option in the Clock Wizard) leads to this VHDL Code

 

clkout1_buf : BUFG
  port map
   (O   => o_CLOCK_Clock0,
    I   => clkout0);

 

and the following Errors:

 

------------------------------------------------------------------------------------------------------------------------------------

ERROR:Place:1205 - This design contains a global buffer instance,
   <CLOCK/clkout1_buf>, driving the net, <top_s_CLOCK_Clock0>, that is driving
   the following (first 30) non-clock load pins off chip.
   < PIN: top_out_VIDEO_Clock.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_Editor.
   < PIN "CLOCK/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >


ERROR:Place:1136 - This design contains a global buffer instance,
   <CLOCK/clkout1_buf>, driving the net, <top_s_CLOCK_Clock0>, that is driving
   the following (first 30) non-clock load pins.
   < PIN: top_out_VIDEO_Clock.O; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue.
   < PIN "CLOCK/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >


ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
------------------------------------------------------------------------------------------------------------------------------------

 

Any ideas what I might do wrong? My hope was to use some kind of buffer (or really any VHDL-based solution) to understand and solve the problem. So your suggestion is most welcome! But unforunately this leads to more errors.

 

 

 

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Xilinx Employee
Xilinx Employee
7,555 Views
Registered: ‎04-16-2012

Re: Place:1198-Error : Route cause and possible solution

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Hi,

Can you please provide a snapshot of the PLL connectivity here before adding BUFG?

Thanks
--------------------------------------------------------------------------------------------
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7,554 Views
Registered: ‎10-23-2013

Re: Place:1198-Error : Route cause and possible solution

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Here you find some snapshots before adding a BUFG. If you need other or specific infomation dont hesitate to ask.

 

2014-01-29_103134.png

 

 

2014-01-29_103448.png

 

 

2014-01-29_103459.png

 

 

2014-01-29_103536.png

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Adventurer
Adventurer
7,516 Views
Registered: ‎07-20-2011

Re: Place:1198-Error : Route cause and possible solution

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engineer_on_tour,

 

This is probably done automatically by synthesizer, but you might need to add an OBUF. This may help (from p.113 of UG382):

 

ug382.png

I think the warning you mentioned, meant something like the configuration obove.

 

Regards

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4,945 Views
Registered: ‎10-23-2013

Re: Place:1198-Error : Route cause and possible solution

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I didn't need to insert an OBUF, but in the PLL instance I needed an BUFG and in the Video-instace an ODDR2.

 

Now everything works fine.

 

  ODDR2_CLK : ODDR2
  generic map(
    DDR_ALIGNMENT => "C0",               -- Sets output alignment to "NONE", "C0", "C1" : as D0 and D1 are constant the allignment does not matter here!
    INIT          => '0', -- Sets initial state of the Q output to '0' or '1'
    SRTYPE        => "ASYNC")             -- Specifies "SYNC" or "ASYNC" set/reset
  port map (
    Q             => out_VIDEO_Clock,   -- 1-bit output data
    C0            => i_CLOCK_VideoClock,   -- 1-bit clock input
    C1            => int_s_VideoClock_n, -- 1-bit clock input
    CE            => '1',  -- 1-bit clock enable input
    D0            => '1',     -- 1-bit data input (associated with C0)
    D1            => '0',     -- 1-bit data input (associated with C1)
    R             => '0',     -- 1-bit reset input
    S             => '0'      -- 1-bit set input
  );

 

 

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Visitor luoyangjin
Visitor
293 Views
Registered: ‎04-01-2018

Re: Place:1198-Error : Route cause and possible solution

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Hello! I also have the same problem when I Implementing Dsign on XC6SLX150. NOw, I have two problems about the resolution: why are there an ODDR2? That is why not the clock signal is output through a BUFG to the output pin? The second one is that I tried the tip deleting the LOC of the output clock in .UCF file and the problem didn't show again, ps: the implementation worked on my board. Do you know why it happens? Can it automotically recognize?

 

Thank you in advance!

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