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Observer amirsadegh
Observer
544 Views
Registered: ‎08-03-2018

Problem with Maximum Number of DCM Delay Steps for Variable Phase Shift

Hi 

I am using spartan 6_XC6SLX9.

In "Spartan-6 FPGA Clocking Resources" doc [UG382] , in page 68, table 2-4 , there is a equation for "Maximum Number of DCM Delay Steps" . In this equation  there is a term "INTEGER" and i did't find it's value.I searched  in this doc and in "DC and Switching Characteristics" doc [DS162] but i did,i find any thing.

Can anyone explain it ??

How can i find it ??

 

Thank you...

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3 Replies
Historian
Historian
526 Views
Registered: ‎01-23-2009

Re: Problem with Maximum Number of DCM Delay Steps for Variable Phase Shift

INTEGER only means to truncate the number to the nearest lower integer value. (i. e. drop the fractional part after the calculation).

 

Avrum 

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Observer amirsadegh
Observer
493 Views
Registered: ‎08-03-2018

Re: Problem with Maximum Number of DCM Delay Steps for Variable Phase Shift

Hi

I did't understand what you mean ... sorry ... can you explain more about this please ??

Thank you for your reply.

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Explorer
Explorer
478 Views
Registered: ‎05-08-2018

Re: Problem with Maximum Number of DCM Delay Steps for Variable Phase Shift

Perhaps I can help,

 

The DCM has a delay line with taps every 35ps.  The delay line is long enough to contain one clock cycle at the minimum frequency specified (~ 20 MHz, or 50ns).  So, if the clock is a much higher frequency (say 500 MHz), the period in the delay line is 2ns worth of taps ~57  (the remainder are not used).

 

So, a step in phase cannot be smaller than 35ps, and the control can only step from >0 degrees, to 360 degrees, regardless of clock frequency.

 

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