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Visitor js12031
Visitor
1,600 Views
Registered: ‎09-27-2017

SelectIO Wizard - Not getting the expected output data

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Hello,

I am using Vivado 2016.4 and working with a XC7A35G 7 Series FPGA. I am using SelectIO ip core to get parallel data from incoming camera LVDS lanes but I don't see the correct data coming out of the SelectIO even though my bitslip is 0. I decided to simulate it to understand this IP core better but even then I do not see the correct output bits from my simulation. This is my waveform. I expected to get 1111111111 at around 305ns but I see 1111000000. The data by clk_1 between 255ns to 305ns, I expected would be shown on the next clkdiv rising edge.

My clk_1 period is 10ns, clkdiv = 50ns, DDR, serialization factor is 10 and external data width 1. I am using internal clock with 0 bitslip and no delays. I have attached a screenshot of the waveform, selectIO settings and my testbench. Can someone please explain why I fail to see the expect output at the rising edge of clkdiv? Thanks in advance.

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selectiosettings.PNG
selectio_waveform.PNG
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1 Solution

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Voyager
Voyager
2,351 Views
Registered: ‎06-24-2013

Re: SelectIO Wizard - Not getting the expected output data

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Hey @js12031,

 

While this result might be unexpected for you, it is not really that unexpected.

 

If you look closely at thre elaborated design or the schematic for the synthesized design, you will see that the lvdsrx core consists of two ISERDES blocks configured in NETWORKING mode which are responsible for the deserialization. Those are specialized resources (hardened IP) inside the FPGA with dedicated connections, little to none documentation about the internals and a lot of secret sauce.

 

The SelectIO Resources User Guide (UG471) says about the reset input ...

The reset signal should only be deasserted when it is known that CLK and CLKDIV are stable and present, and should be a minimum of two CLKDIV pulses wide. After deassertion of reset, the output is not valid until after two CLKDIV cycles.

 

There is no relation given between sampled data and output bits though, instead the bitslip module is 'available' and adds some latency to the sampled data. In short, to have reliable deserialization you need some kind of training to word align the output in this mode.

 

Here is your wave form with the bit order reversed (LSB to MSB) and shifted by the offset of the deserializer ...

selectio_waveform.png

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
3 Replies
Voyager
Voyager
2,352 Views
Registered: ‎06-24-2013

Re: SelectIO Wizard - Not getting the expected output data

Jump to solution

Hey @js12031,

 

While this result might be unexpected for you, it is not really that unexpected.

 

If you look closely at thre elaborated design or the schematic for the synthesized design, you will see that the lvdsrx core consists of two ISERDES blocks configured in NETWORKING mode which are responsible for the deserialization. Those are specialized resources (hardened IP) inside the FPGA with dedicated connections, little to none documentation about the internals and a lot of secret sauce.

 

The SelectIO Resources User Guide (UG471) says about the reset input ...

The reset signal should only be deasserted when it is known that CLK and CLKDIV are stable and present, and should be a minimum of two CLKDIV pulses wide. After deassertion of reset, the output is not valid until after two CLKDIV cycles.

 

There is no relation given between sampled data and output bits though, instead the bitslip module is 'available' and adds some latency to the sampled data. In short, to have reliable deserialization you need some kind of training to word align the output in this mode.

 

Here is your wave form with the bit order reversed (LSB to MSB) and shifted by the offset of the deserializer ...

selectio_waveform.png

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
Visitor js12031
Visitor
1,503 Views
Registered: ‎09-27-2017

Re: SelectIO Wizard - Not getting the expected output data

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Thank you for your help hpoetzl, 

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Voyager
Voyager
1,472 Views
Registered: ‎06-24-2013

Re: SelectIO Wizard - Not getting the expected output data

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You're welcome!

 

All the best,

Herbert

-------------- Yes, I do this for fun!
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