11-14-2018 08:24 PM
I have an application the may possibly benefit from more efficient uses of resources by utilising the DSP blocks to perform an XOR operation rather than it being done in regular logic.
While I have found the USR-DSP48 directive in the Vivado Synthesis guide, I can't find any real information on how this mechanism actually works, how fast it is, how much logic it uses, how many clock cycles it takes to do an operation etc etc.
Can someone please point me in the direction of some detailed documentation for the USE_DSP48 = "logic" directive please.
11-15-2018 12:47 AM - edited 11-15-2018 02:32 AM
Please always ask a high quality question. Stackoverflow has a really good guide about this topic.
11-15-2018 02:46 AM
Thanks for the reply and the pointers. I had a feeling that when I posted the question I wasn't giving enough info!
I'm using an Artix 7-200T - I believe it's specifically an XC7A200TFBG484-2.
The guide I was referring to is this one here - "Vivado Design Suite User Guide Synthesis" - https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_3/ug901-vivado-synthesis.pdf
I have studied those pages in the "7 Series DSP48E1 Slice user Guide" document, I am yet to find an obvious answer to my original question but i am sure it is in there once I understand how to interpret the info. The logic in there doesn't appear to be synchronously clocked (at first glance) so I guess it's just a case of doing a timing analysis in Vivado to see how fast the DSP units are compared to using regular logic elements.
Thanks again for the response!