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Contributor
Contributor
1,098 Views
Registered: ‎07-04-2017

Using memory values in Verilog / VHDL

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Hello everyone,

 

I'm using Zybo and i want to create a custom ip. The ip will have two inputs (as registers) that has 32 bits: Let's call them a[31:0] and  b[31:0]. And i want to get memory value at a and add b. The calculated value is a new memory address and i want to read value at that address and write it into the third register of ip. But i haven't find a tutorial like this. If there's any, i would like to know it.

 

Thanks for your time.

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Scholar hbucher
Scholar
1,393 Views
Registered: ‎03-22-2016

Re: Using memory values in Verilog / VHDL

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@ercumentkaya  It does not matter zybo or any other board. This part is all the same.

So you mentioned "address" and "verilog". So I assume that you need to be using the AXI MM protocol.  If that is your goal though, here is a tutorial and some videos we made

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_3/ug1119-vivado-creating-packaging-ip-tutorial.pdf

http://www.vitorian.com/x1/archives/609

 

The AXI protocol is quite heavy for this kind of task. Some alternatives: 

- do in verilog but use registers instead (http://www.science.smith.edu/dftwiki/index.php/Xilinx_ISE_Four-Bit_Adder_in_Verilog)

- create a vivado HLS component that takes a master axi interface (http://www.vitorian.com/x1/archives/594)

- use the Zynq PS and write it in C

 

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3 Replies
Scholar hbucher
Scholar
1,081 Views
Registered: ‎03-22-2016

Re: Using memory values in Verilog / VHDL

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@ercumentkaya The problem here is not the sum, but retrieving and storing the values. 

Where are your reading/writing from/to? What interfaces you have to contend with? AXI MM? AXI Lite? AXI Stream? BRAM? 

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.
Contributor
Contributor
1,079 Views
Registered: ‎07-04-2017

Re: Using memory values in Verilog / VHDL

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@hbucher Thank you for your reply. Actually I'm new to zybo. I want to use OCM which is 512 MB if it's possible.

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Scholar hbucher
Scholar
1,394 Views
Registered: ‎03-22-2016

Re: Using memory values in Verilog / VHDL

Jump to solution

@ercumentkaya  It does not matter zybo or any other board. This part is all the same.

So you mentioned "address" and "verilog". So I assume that you need to be using the AXI MM protocol.  If that is your goal though, here is a tutorial and some videos we made

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_3/ug1119-vivado-creating-packaging-ip-tutorial.pdf

http://www.vitorian.com/x1/archives/609

 

The AXI protocol is quite heavy for this kind of task. Some alternatives: 

- do in verilog but use registers instead (http://www.science.smith.edu/dftwiki/index.php/Xilinx_ISE_Four-Bit_Adder_in_Verilog)

- create a vivado HLS component that takes a master axi interface (http://www.vitorian.com/x1/archives/594)

- use the Zynq PS and write it in C

 

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.