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Observer bujosa
Observer
5,737 Views
Registered: ‎05-24-2011

Virtex 7 MIG 7 series options

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xc7vx485tffg1157-2

ise 13.2

 

The MIG version 1.2 coregen for ddr3 does not have multi controller or debug port options.  Will they eventually be coming back?

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Xilinx Employee
Xilinx Employee
7,194 Views
Registered: ‎10-23-2007

Re: Virtex 7 MIG 7 series options

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Yes.

 

These features will roll into the upcoming releases, but I can't say specifically when.

 

In the meantime, you can run MIG multiple times for the multicontroller issue.  Not as nice, but you can get the job done since the controllers basically operate independently.

 

And if you are one of the lucky users with silicon, then you likely already have a good support channel and you should be able to get your debug port questions answered.

 

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Xilinx Employee
Xilinx Employee
7,195 Views
Registered: ‎10-23-2007

Re: Virtex 7 MIG 7 series options

Jump to solution

Yes.

 

These features will roll into the upcoming releases, but I can't say specifically when.

 

In the meantime, you can run MIG multiple times for the multicontroller issue.  Not as nice, but you can get the job done since the controllers basically operate independently.

 

And if you are one of the lucky users with silicon, then you likely already have a good support channel and you should be able to get your debug port questions answered.

 

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Newbie rcheerla
Newbie
5,628 Views
Registered: ‎10-18-2011

Re: Virtex 7 MIG 7 series options

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I tried running the MIG multiple times and the design gets over-written.

Can you publish the steps to create a multi-controller design ? Some detail here would help me correct my mistake.

 

Thanks.

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