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Observer bujosa
Observer
6,121 Views
Registered: ‎05-24-2011

Virtex 7 pcie coregen broken

Jump to solution

xc7vx485tffg1157-2

ise 13.2

 

I created a 1 lane pcie core in coregen  (there is only one version)

 

Problem 1:

In implement/synplify.prj it is looking for "source/gtx_wrapper" but only "source/gt_wrapper" exists. I changed synplify.prj to look for gt_wrapper and move on.

 

Problem 2:

in implement/synplify.prj it is looking for -top_module  "xilinx_pcie_2_0_ep_7x" but only "xilinx_pcie_2_1_ep_7x" exists.  I change synplify.prj to look for xilinx_pcie_2_1_ep_7x and move on.

 

Problem 3:

@E: CG596
:"/vobs/j750/tomahawk/cash/syn/cash_7vx485/ipcore_dir/pcie_7vx485/source/gt_wrapper.v":929:9:929:17|parameter
RXOUT_DIV cannot be found in module GTXE2_CHANNEL.

The parameter "PCIE_GT_DEVICE = "GTX"

 

In the file gt_wrapper.v there is a module called GTXE2_CHANNEL with a parameter .RXOUT_DIV.  

 

Not sure what to do at this point.  Any ideas?

 

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
7,617 Views
Registered: ‎11-28-2007

Re: Virtex 7 pcie coregen broken

Jump to solution

In general new cores or cores migrated to a new device family are initially available in one HDL (Verilog or VHDL) and only tested in xst flow. The other HDL and Synplify flow will be added as the cores become stable. On the other hand, the tool shouldn't produce something that doesn't work. Please open a webcase with the tech support.

 

Regarding your question about the RXOUT_DIV port, you will need the latest Synplify version E201103SP2 to work with 13.2 because several port names of some primitives changed in 13.2, but older synplify versions didn't have the new port names.

 


@bujosa wrote:

xc7vx485tffg1157-2

ise 13.2

 

I created a 1 lane pcie core in coregen  (there is only one version)

 

Problem 1:

In implement/synplify.prj it is looking for "source/gtx_wrapper" but only "source/gt_wrapper" exists. I changed synplify.prj to look for gt_wrapper and move on.

 

Problem 2:

in implement/synplify.prj it is looking for -top_module  "xilinx_pcie_2_0_ep_7x" but only "xilinx_pcie_2_1_ep_7x" exists.  I change synplify.prj to look for xilinx_pcie_2_1_ep_7x and move on.

 

Problem 3:

@E: CG596
:"/vobs/j750/tomahawk/cash/syn/cash_7vx485/ipcore_dir/pcie_7vx485/source/gt_wrapper.v":929:9:929:17|parameter
RXOUT_DIV cannot be found in module GTXE2_CHANNEL.

The parameter "PCIE_GT_DEVICE = "GTX"

 

In the file gt_wrapper.v there is a module called GTXE2_CHANNEL with a parameter .RXOUT_DIV.  

 

Not sure what to do at this point.  Any ideas?

 




Cheers,
Jim
2 Replies
Xilinx Employee
Xilinx Employee
7,618 Views
Registered: ‎11-28-2007

Re: Virtex 7 pcie coregen broken

Jump to solution

In general new cores or cores migrated to a new device family are initially available in one HDL (Verilog or VHDL) and only tested in xst flow. The other HDL and Synplify flow will be added as the cores become stable. On the other hand, the tool shouldn't produce something that doesn't work. Please open a webcase with the tech support.

 

Regarding your question about the RXOUT_DIV port, you will need the latest Synplify version E201103SP2 to work with 13.2 because several port names of some primitives changed in 13.2, but older synplify versions didn't have the new port names.

 


@bujosa wrote:

xc7vx485tffg1157-2

ise 13.2

 

I created a 1 lane pcie core in coregen  (there is only one version)

 

Problem 1:

In implement/synplify.prj it is looking for "source/gtx_wrapper" but only "source/gt_wrapper" exists. I changed synplify.prj to look for gt_wrapper and move on.

 

Problem 2:

in implement/synplify.prj it is looking for -top_module  "xilinx_pcie_2_0_ep_7x" but only "xilinx_pcie_2_1_ep_7x" exists.  I change synplify.prj to look for xilinx_pcie_2_1_ep_7x and move on.

 

Problem 3:

@E: CG596
:"/vobs/j750/tomahawk/cash/syn/cash_7vx485/ipcore_dir/pcie_7vx485/source/gt_wrapper.v":929:9:929:17|parameter
RXOUT_DIV cannot be found in module GTXE2_CHANNEL.

The parameter "PCIE_GT_DEVICE = "GTX"

 

In the file gt_wrapper.v there is a module called GTXE2_CHANNEL with a parameter .RXOUT_DIV.  

 

Not sure what to do at this point.  Any ideas?

 




Cheers,
Jim
Xilinx Employee
Xilinx Employee
6,018 Views
Registered: ‎04-06-2010

Re: Virtex 7 pcie coregen broken

Jump to solution

Did you make sure to use the latest patch?  You can find it here:

http://www.xilinx.com/support/answers/43949.htm

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