03-08-2017 10:16 PM
In vivado 2015.4 , I generate the AXI Interconnect IP core, 6 master and 1 slave .
The resource is so large about 9000 slice or more ,and the MIG about 3500 slice.
A7 100T has 15850 slices total,there is nothing left for user to use!!
The AXI Interconnect must use so many resource?
03-09-2017 01:10 AM
What bit-widths are you using? That does seem like a very excessive amount of hardware; I've never seen an interconnect so large.
03-17-2017 01:59 PM
I'm surprised an interconnect 512 bits wide is that small ...
Reduce the width on the MIG, the crossbar will shrink accordingly.
If you run MIG as 32 bit the crossbar should be tiny, and the width converter pieces of it should go away (if they don't, delete and re-add the interconnect).
03-18-2017 06:31 AM
Yes, cut down the bus width. If necessary turn up the clock speed to compensate - but keep an eye on how much bandwidth actually makes sense.
If you've got a 32-bit connection between the MIG and some DDR RAM at 1000Mbps. That gives a total bandwidth of 32000Mbps. If you use a 128-bit connection to the MIG then it'll have to run at 250MHz, and that's probably manageable in the Artix fabric. A 256-bit connection at 125MHz would definitely be OK.